ASIC Interface Controller for Low Latency Mesh Routing
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Solution Overview
Problem
Existing mesh networks face performance degradation due to increased network traffic, particularly in real-time services like VoIP, as they incur significant packet forwarding delays, limiting the network to about 8 hops due to computing overhead, which is inadequate for scalable and efficient communication.
Innovation Solution
An interface controller implemented as an Application Specific Integrated Circuit (ASIC) with programmable building blocks, comprising MAC and Network Processor cores, optimized for low power consumption and fast packet forwarding, capable of handling up to 10,000 nodes with reduced latency, enabling efficient routing and minimizing host processor involvement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If mesh networks use standard packet forwarding with host processor involvement, then routing flexibility is maintained, but packet forwarding latency increases significantly
Solution Approach 1:
The patent extracts packet forwarding functionality from the host processor into a dedicated network processor core. This separate core handles packet routing independently, removing the latency burden from the host processor while maintaining routing flexibility through programmable logic.
Solution Approach 2:
The network processor core acts as an intermediary between the host processor and network interfaces. It handles time-critical packet forwarding operations, allowing the host processor to focus on higher-level tasks while ensuring low-latency packet handling through specialized processing.
2Quantity of substance
If mesh networks support more hops to increase node capacity, then network scalability improves, but packet forwarding delays accumulate
Solution Approach 1:
The patent segments the network processing function into distributed network processor cores at each node. Each core independently handles packet forwarding with minimal delay, allowing packets to traverse many hops (100+) without cumulative latency degradation that would occur with centralized host processor handling at each node.
Solution Approach 2:
The network processor core performs packet forwarding in advance of host processor intervention. By handling routing decisions and packet transmission before higher-level processing is needed, the system minimizes per-hop latency and enables support for extensive multi-hop networks.
3Adaptability or versatility
If full-featured network processors are used to handle complex routing, then routing capability is enhanced, but power consumption increases
Solution Approach 1:
The patent segments network processing into two parts: a lightweight network processor core for time-critical packet forwarding operations, and a full-featured host processor for higher-level networking tasks. This segmentation allows the system to use minimal power for routine packet handling while retaining full routing capability when needed.
Solution Approach 2:
The network processor core provides localized, optimized processing for packet forwarding at each network node. Instead of using full-power processors at every node, the system applies processing power locally only where and when needed, reducing overall network power consumption while maintaining routing versatility.
Data Source
AI summary
An improved micro architectural approach for a network microprocessor has low power consumption, and employs two specialized processing cores, a MAC processing core and a network processor core. Each of these processing cores has facilities designed for a specific set of functions, to handle ISO layer 2 and layer 3 functionality in a packet switched Software Defined Radio mobile network.