ASIC Design Reuse via IP Extraction and Packaging
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Solution Overview
Problem
Conventional design flows for ASICs do not allow for efficient reuse of customer-designed logic, requiring re-running of all implementation stages for subsequent designs that share intellectual property, leading to inefficiency and increased design-timing closure complexity.
Innovation Solution
A design tool comprising an input module, generation module, synthesis module, and extraction module that enables the creation and reuse of soft, firm, and hard intellectual property by automatically extracting and packaging design information, allowing customers to design IP once and reuse it in subsequent designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional design flow is used where all customer designed logic is treated as raw RTL, then the design process is simple and uniform, but design reuse is not enabled and all implementation stages must be re-run for subsequent designs
Solution Approach 1:
The system performs preliminary analysis of customer-designed logic to identify and extract reusable IP blocks before the main design flow proceeds. This advance preparation enables subsequent designs to reuse these extracted IP blocks without re-running implementation stages, directly resolving the time loss contradiction.
Solution Approach 2:
The system extracts reusable intellectual property blocks from customer-designed logic by analyzing design hierarchy, interface definitions, and functionality. This extraction creates standalone IP artifacts that can be reused in subsequent designs, enabling design reuse capability while reducing implementation time.
2Reliability
If all stages of implementation flow are re-run for subsequent designs that share IP, then complete design verification is achieved, but the process is inefficient and time-consuming
Solution Approach 1:
The implementation flow is segmented into reusable IP extraction phase and subsequent design integration phase. The extracted IP blocks are verified once and then reused across multiple designs, maintaining verification completeness while improving productivity by avoiding redundant verification of the same IP blocks.
Solution Approach 2:
The system creates copyable IP artifacts from customer-designed logic that can be instantiated multiple times in subsequent designs. These IP copies maintain the verified functionality of the original design while enabling efficient reuse, thus preserving reliability while enhancing productivity.
3Loss of time
If customer designed IP is reused in subsequent designs, then design time is reduced, but design-timing closure becomes more complicated with longer run time during placement and optimization
Solution Approach 1:
The system performs preliminary extraction and characterization of IP blocks with their timing constraints and interface definitions before reuse. This preliminary preparation includes generating accurate timing models that simplify subsequent placement and optimization, reducing timing closure complexity despite using reused IP.
Solution Approach 2:
The system introduces an IP extraction and characterization intermediary layer between the original design and subsequent reuse instances. This intermediary prepares standardized IP artifacts with complete timing information, which mediates the complexity of timing closure by providing pre-analyzed timing models that simplify placement and optimization in subsequent designs.
Data Source
AI summary
A design tool for generating design views of a semiconductor chip is presented. The design tool includes an input module, a generation module, a first synthesis module, a user interface module and an extraction module. The input module may be configured to receive input including physical and logical resources and a custom chip specification. The generation module may be configured to generate Register Transfer Level (RTL) views for the semiconductor chip. The first synthesis module may be configured to perform logic synthesis using the RTL views. The user interface module may be configured to query a user whether re-usable intellectual property (IP) is to be generated. The extraction module may be configured to extract and package design information for the re-usable IP in response to a request from the user.