ASIC LUT Mapping With Area-Aware Logic Optimization
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Solution Overview
Problem
Existing ASIC synthesis methods using lookup tables (LUTs) are not optimized for standard cells, leading to larger area and higher power consumption, as they are based on the fixed area of LUTs in FPGAs rather than the variable area of standard cells in ASICs.
Innovation Solution
The approach involves mapping a logic network to a network of LUTs, estimating and optimizing their areas using Boolean optimization techniques, and then reducing them to a gate-level netlist of standard cells, considering the differences between FPGAs and ASICs, such as area estimation based on literal counts and AIG representations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If LUT mapping is performed using fixed area assumptions from FPGAs, then the mapping process is simple, but the area occupied by components in the netlist increases
Solution Approach 1:
The patent changes the area estimation parameter from fixed LUT area (FPGA approach) to variable area based on literal counts and AIG representations (ASIC approach). This allows the area estimation to adapt to the specific logic function being implemented, resulting in more accurate area calculations and optimized netlist area for ASIC technology.
Solution Approach 2:
The patent introduces dynamic area estimation that adapts to different logic functions and their implementations. Instead of using a static fixed area value for all LUTs, the system dynamically calculates area based on the actual logic complexity (literal counts, AIG node counts) of each function, enabling optimized resource allocation in the netlist.
2Device complexity
If LUT mapping is performed using fixed area assumptions from FPGAs, then the mapping process is simple, but power consumption increases
Solution Approach 1:
The patent changes the estimation parameters to include metrics that correlate with power consumption, such as literal counts and AIG node counts. These parameters provide a more accurate representation of the actual logic complexity and switching activity, enabling power-optimized netlist generation for ASIC technology.
Solution Approach 2:
The patent introduces dynamic power estimation that adapts to the specific logic functions being mapped. By calculating area and power based on actual logic complexity rather than fixed assumptions, the system can optimize both area and power consumption simultaneously for ASIC implementations.
3Device complexity
If standard LUT optimization techniques are used, then the optimization process is straightforward, but area efficiency decreases
Solution Approach 1:
The patent changes the optimization criteria from generic LUT optimization to ASIC-specific optimization using literal counts and AIG representations. This allows the optimization process to target the specific characteristics of ASIC technology, resulting in improved area efficiency and better netlist quality.
Solution Approach 2:
The patent segments the optimization process into distinct phases: LUT mapping with area estimation, LUT optimization using Boolean techniques, and reduction to gate-level netlist. Each phase uses ASIC-specific parameters and metrics, allowing for targeted optimization at each stage of the synthesis process.
Data Source
AI summary
A logic network for an integrated circuit is synthesized as follows. The logic network is mapped to a network of lookup tables (LUTs). The LUT mapping is based at least in part on estimated areas of the LUTs. The individual LUTs in the network are improved (LUT optimization), for example using various Boolean optimization techniques. The network of improved LUTs is then reduced to a gate-level netlist of standard cells.