Structured ASIC Fabric Using Non-Adjacent Via Layers
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Solution Overview
Problem
Current structured ASICs face challenges in reducing non-recurring expenses (NRE) and turnaround time due to limitations in place and route tools, which restrict metal layer routing and via layer connections, and require custom libraries and additional characterization, making single via configuration with embedded distributed SRAM costly and time-consuming.
Innovation Solution
An architecture that uses two non-adjacent via configuration layers and access wires on horizontal metal routing layers, allowing customers to utilize their existing standard-cell libraries without requiring new transistor layouts or distributed SRAM, thereby reducing the need for custom masks and characterization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If single via configuration with embedded distributed SRAM is used, then the number of custom masks is reduced, but the device complexity and characterization requirements increase
Solution Approach 1:
The patent extracts the configuration function from a single via layer and distributes it across multiple non-adjacent via layers. This allows the device to maintain low mask count benefits while eliminating the need for complex embedded distributed SRAM and custom library characterization, as the configuration is achieved through standard-cell libraries with fixed metal routing layers and selective via connectivity.
Solution Approach 2:
The patent segments the configuration function across multiple non-adjacent via layers (VIA23, VIA45, etc.) rather than using a single via layer. This segmentation allows different via layers to handle different routing grids, reducing the complexity requirements while maintaining the ability to configure the device with fewer custom masks.
2Adaptability or versatility
If place and route tools are used with standard-cell libraries, then routing flexibility is improved, but the turnaround time and NRE costs increase
Solution Approach 1:
The patent applies preliminary action by pre-defining fixed metal routing layers and standard-cell libraries before the configuration process. This allows place and route tools to work with predetermined structures, reducing turnaround time while maintaining routing flexibility through the selective configuration of via layers that connect these pre-established routing grids.
3Adaptability or versatility
If multiple adjacent via layers are used for configuration, then routing connectivity is improved, but the mask cost and fabrication complexity increase
Solution Approach 1:
The patent transitions from using adjacent via layers in a single continuous dimension to using non-adjacent via layers distributed across multiple routing grids. This dimensional change allows each via layer to serve specific routing needs without requiring all adjacent layers to be customized, thereby reducing mask costs while maintaining routing connectivity through the distributed via configuration.
Data Source
AI summary
An application-specific integrated circuit (ASIC) is customized using two non-adjacent via layers. An array of logic cells, each including a plurality of logic devices, are arranged in a plurality of non-customized base layers. A first routing grid, which includes a first non-customized metal routing layer, a customized via layer, and a second non-customized metal routing layer, is disposed on top of the plurality of non-customized layers. A second routing grid, which includes a third non-customized metal routing layer, another customized via layer, and a fourth non-customized metal routing layer, is disposed above the first routing grid. A non-customized via layer is disposed above the first routing grid and beneath the second routing grid. The routing grids and the non-customized via layer collectively facilitate routing connections to and from the logic cells.