Phase-Shifted ASIC Clock Domains for Resonant Noise Reduction
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Solution Overview
Problem
Synchronous digital logic devices face issues with clock drift and resonant circuit noise due to synchronized transistor state transitions, leading to increased power consumption and complexity, especially in modern digital devices with high transistor density.
Innovation Solution
Divide clock domains into phase-shifted-clock domains, where each domain operates at the same frequency but with a phase shift relative to a common reference clock, reducing transistor resonance and power consumption by staggering state transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous circuits use a single global clock to synchronize multiple blocks, then clock drift problems are avoided, but resonant circuit noise increases due to large numbers of transistors toggling at once
Solution Approach 1:
The patent divides the single global clock domain into multiple phase-shifted clock domains. Each domain uses a local clock that is phase-shifted relative to the global clock, allowing transistors in different domains to toggle at different times. This segmentation reduces the simultaneous switching activity that causes resonant noise while maintaining synchronization through the phase-shifted clock structure.
Solution Approach 2:
The patent employs periodic phase-shifted clocks derived from the global clock, where each local clock operates at the same frequency but with a different phase offset. This periodic action distributes transistor switching events across different time phases, reducing peak noise while maintaining the rhythmic synchronization needed for reliable operation.
2Productivity
If clock frequency is increased to improve performance, then productivity increases, but resonant circuit noise and power consumption increase
Solution Approach 1:
By segmenting the clock domain into phase-shifted sub-domains, the patent allows higher clock frequencies to be used without proportionally increasing resonant noise. The phase shifts distribute the high-frequency switching events across different time phases, reducing the constructive interference that causes noise while maintaining the high productivity benefits of increased clock frequency.
3Object-generated harmful factors
If multiple independent local clocks are used in different blocks, then resonant noise is reduced, but clock drift requires inefficient rebuffering operations
Solution Approach 1:
The patent introduces phase-shifted clocks as intermediaries between the global clock and local block clocks. These intermediary clocks maintain a deterministic phase relationship with the global clock, eliminating drift issues while still distributing switching events to reduce noise. This avoids the need for complex rebuffering operations that would be required with completely independent clocks.
Data Source
AI summary
An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.