ASIC Package Photonics and Vertical Power Delivery for High-Speed I/O
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Solution Overview
Problem
Input/output (I/O) systems connecting application-specific integrated circuit (ASIC) packages with other components often experience insufficient bandwidth, leading to bottlenecks that limit the ASIC die's operational potential due to signal loss and increased power consumption.
Innovation Solution
The integration of photonic modules and a vertically integrated power regulator into the ASIC package, along with serializer/deserializer (SerDes) interfaces, reduces signal loss and power consumption by minimizing trace length and optimizing power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional I/O systems are used to connect ASIC packages with other components, then the system structure is simple, but the bandwidth is insufficient and signal loss increases
Solution Approach 1:
The patent replaces traditional electrical signal transmission through copper traces with optical signal transmission through photonic modules. This substitution eliminates the limitations of electrical signal degradation over distance, achieving lower signal loss and higher bandwidth while maintaining system reliability.
Solution Approach 2:
The patent transitions from planar copper trace routing to three-dimensional photonic integration, where optical signals can be transmitted through waveguides and vertical couplers. This dimensional change enables shorter transmission paths and reduced signal loss while increasing bandwidth capacity.
2Ease of manufacture
If copper traces are used for SerDes interfaces, then the connection is simple, but copper losses increase and heat generation occurs
Solution Approach 1:
The patent replaces copper trace-based electrical connections with photonic waveguide-based optical connections. While photonic module integration is more complex than copper trace deposition, the overall system achieves lower energy losses and reduced heat generation, offsetting the manufacturing complexity through improved performance.
Solution Approach 2:
The patent changes the fundamental transmission medium from electrical conductors (copper) to optical waveguides (photonic materials). This parameter change transforms the transmission mechanism from electrical current flow to light propagation, dramatically reducing resistive losses and heat generation in the SerDes interfaces.
3Power
If power is delivered through traditional horizontal traces, then the power delivery network is simple, but signal loss and power consumption increase
Solution Approach 1:
The patent implements vertical power delivery through stacked substrates and via holes, transitioning from horizontal power distribution to three-dimensional vertical routing. This dimensional change shortens the length of power traces, reduces resistive losses, and improves power delivery efficiency while lowering overall power consumption.
Solution Approach 2:
The patent segments the power delivery network into multiple stacked layers, with power and ground planes distributed across different substrates. This segmentation allows for optimized local power delivery to different functional blocks, reducing the total trace length and minimizing power losses in each segment.
4Adaptability or versatility
If long copper traces are used for high-speed I/O, then the layout is flexible, but signal loss increases significantly
Solution Approach 1:
The patent replaces long copper traces with photonic waveguides that can route optical signals through three-dimensional space. This substitution maintains layout flexibility through waveguide routing while dramatically reducing signal loss, as optical signals do not suffer from the same resistive and capacitive effects that limit copper trace performance at high speeds.
Data Source
AI summary
The technology relates to an integrated circuit (IC) package. The IC package may include a substrate. An IC die may be mounted to the substrate. One or more photonic modules may be attached to the substrate and one or more serializer/deserializer (SerDes) interfaces may connect the IC die to the one or more photonic modules. The IC die may be an application specific integrated circuit (ASIC) die and the one or more photonic modules may include a photonic integrated circuit (PIC) and fiber array. The one or more photonic modules may be mounted to one or more additional substrates which may be attached to the substrate via one or more sockets.


