Automated Control Code Generation for ASICs and PLDs
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Solution Overview
Problem
Conventional design and verification methodologies for complex System-on-Chip (SoC) and Programmable Logic Devices (PLDs) are time-consuming and prone to inconsistencies, especially with large teams involved, and manual approaches can miss errors due to the complexity of register verification and lack of standardized documentation.
Innovation Solution
An automated system for generating control and monitor code using a specification file that allows inputting control/monitor structures, automatically populating fields, detecting and correcting errors, and generating RTL abstraction code, design verification files, and documentation, supporting multiple types of control/monitor structures and interrupt registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manual approaches are used for register verification and code generation, then flexibility and adaptability are maintained, but time consumption increases significantly and errors are more likely to occur
Solution Approach 1:
The system enables self-service automation where the specification file automatically generates control/monitor code, verification code, and documentation without requiring manual intervention in the code generation process. The automated code generator reads the specification file and produces all necessary artifacts, eliminating the need for manual coding while maintaining accuracy through systematic generation based on the specification.
Solution Approach 2:
The patent replaces manual mechanical processes (hand-writing code, manually updating documentation, manual verification) with an automated computational system. The automated code generator uses software algorithms to read the specification file and generate code, replacing the mechanical act of manual writing and editing with automated computational generation, thereby significantly increasing productivity.
2Reliability
If manual updates are made to test bench components when register specifications change, then adaptability to design changes is maintained, but time consumption increases and inconsistencies are more likely to occur
Solution Approach 1:
The system implements feedback mechanisms where changes to the specification file automatically trigger regenerative updates of the control/monitor code, verification code, and documentation. This feedback loop ensures that any modification to register specifications is immediately reflected across all related artifacts, maintaining consistency without requiring manual coordination between different team members.
Solution Approach 2:
The specification file serves as a centralized master definition that is updated in advance before code generation. By maintaining the specification as the single source of truth and regenerating all dependent artifacts from it, the system performs preliminary organization of information that prevents inconsistencies from arising in the first place, rather than requiring reactive updates afterward.
3Manufacturing precision
If standardized templates are used for control/monitor structures, then consistency and accuracy are improved, but flexibility in handling custom designs is reduced
Solution Approach 1:
The specification file format is designed to be universal, accommodating a wide variety of control/monitor structures, register configurations, and device types through a single standardized template system. The template framework can handle different device architectures (ASICs, FPGAs, PLDs) and custom designs by allowing flexible population of parameters while maintaining the same overall structure, thereby achieving both standardization and adaptability.
Solution Approach 2:
The system maintains flexibility through parameterizable templates where specific values can be changed based on the particular design requirements. Instead of requiring different templates for different designs, the same template framework allows parameter modification (such as register addresses, data widths, access modes) to accommodate custom designs, thereby achieving both consistency through standardization and flexibility through parameterization.
Data Source
AI summary
Systems and methods for automated control/monitoring code development for ASICs and PLDs are provided. Control/monitor structures associated with a module may be inputted into a standard specification file. One or more default configurations for each control/monitor structure may also be inputted into the specification file. Fields of the specification file may be automatically populated or updated in response to user input in another field, and input and consistency errors may be automatically detected and/or corrected. After a request to build a module is received, one or more source or header output files may be automatically generated using information from the specification file. Automatically generated documentation may also be inserted into the output files, and links may be generated to and from hardware specifications and programmer's manuals.