ASIC Power Delivery via Vertical Power Block PCB
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Solution Overview
Problem
Transporting high current power into the center of an ASIC for core and SERDES power is burdensome due to layer count and power plane resistance issues, leading to increased costs and complexity in printed circuit board design.
Innovation Solution
The solution involves a main printed circuit board with an open section in the center, where a power block printed circuit board is inserted from below to provide power directly to the ASIC, reducing the need for lateral power routing through the main board layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power is transported laterally through the main PCB layers into the center of the ASIC, then power can be delivered to the ASIC core, but the layer count increases and power plane resistance increases
Solution Approach 1:
The power delivery system is segmented into two independent parts: the main PCB handling signal routing and a separate power block PCB handling power delivery. This segmentation allows each subsystem to be optimized independently, reducing the layer count burden on the main PCB while maintaining high current power delivery capability to the ASIC core.
Solution Approach 2:
The invention transitions from lateral power routing within the PCB plane to vertical power delivery through a dedicated power block PCB positioned beneath the ASIC. This dimensional change allows power to be delivered from the bottom up, bypassing the need for extensive lateral power planes in the main PCB layers.
2Power
If power is transported laterally through the main PCB layers into the center of the ASIC, then power can be delivered to the ASIC core, but power plane resistance increases
Solution Approach 1:
By segmenting the power delivery function into a separate power block PCB, the invention creates dedicated low-resistance power paths that are optimized for high current flow. This separates the power delivery function from the signal routing function, allowing each to be optimized independently for its specific performance requirements.
Solution Approach 2:
The power block PCB acts as an intermediary between the power source and the ASIC core, providing a low-resistance connection path. This intermediary structure reduces the overall power plane resistance by creating a direct vertical power delivery path rather than relying on lateral routing through multiple PCB layers.
3Power
If additional PCB layers are added for power transport, then power delivery to ASIC core is enabled, but production cost increases
Solution Approach 1:
The invention segments the PCB into two functional blocks: a standard main PCB for signal routing and a specialized power block PCB for power delivery. This segmentation allows the main PCB to be manufactured with fewer layers, reducing its complexity and cost, while the power block PCB can be optimized specifically for power delivery requirements.
Solution Approach 2:
The power delivery function is extracted from the main PCB and placed into a separate power block PCB. This extraction reduces the layer count and complexity of the main PCB, thereby lowering its manufacturing cost, while the dedicated power block can be designed and manufactured independently with optimal power delivery characteristics.
Data Source
AI summary
Techniques to move high current power distribution layers for integrated circuit core power and serializer-deserializer (SERDES) power into a center area of the integrated circuit footprint. This provides a more reliable and higher current distribution into the center of a large integrated circuit footprint, without causing disruption of high speed signal routing or increased signal integrity burden to the high speed signals. Arrangements and methods for routing out the core power area of a main printed circuit board under an integrated circuit and replacing it with a custom power printed circuit board (power plug) that is attached by a metalized paste sintering process. This provides a more reliable and higher current distribution into the center of a large integrated circuit or other high-power component, without causing disruption of high speed signal routing.