ASIC Protocol Stack Hardware Acceleration

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Solution Overview

Problem

In MediaFLO™ mobile multimedia multicast systems, the software-based protocol stack processing consumes significant CPU cycles and memory, leading to increased power consumption and overhead, particularly due to operations like CRC checking, defragmentation, and decryption, which compete with other applications and shorten battery life.

Innovation Solution

The implementation of hardware components within the ASIC memory to perform protocol stack processing, including deinterleaving, Reed-Solomon decoding, decryption, and CRC processing, reduces the burden on the host processor and optimizes data transfer by processing data in place, minimizing memory usage and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If software-based protocol stack processing is used, then flexibility and ease of implementation are improved, but CPU cycle consumption and power consumption increase significantly

Engineering Contradiction:

Improveease of implementationVSAvoidpower consumption

Core Design Contradiction:

Ease of manufactureVSUse of energy by moving object

Solution Approach 1:

The patent replaces software-based protocol stack processing with hardware-based processing using dedicated ASIC components. Specifically, the MAC layer core, stream layer core, decryption layer core, defragmentation layer core, and sync layer core are implemented as hardware modules within the ASIC memory, substituting the mechanical/software processing system with a hardware-based system that consumes less power while maintaining implementation flexibility through configurable hardware designs.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Adaptability or versatility

If software-based protocol stack processing is used, then adaptability to different protocols is improved, but processing speed and productivity deteriorate

Engineering Contradiction:

Improveprotocol adaptabilityVSAvoidprocessing speed

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments the protocol stack processing into distinct functional cores within the ASIC: MAC layer core for deinterleaving and Reed-Solomon decoding, stream layer core for extraction and decryption key management, decryption layer core for decryption operations, defragmentation layer core for CRC processing and packet construction, and sync layer core for header parsing. This segmentation enables parallel processing of different protocol layers, significantly improving processing speed while maintaining adaptability through configurable hardware modules.

Inventive Principle:

Principle #1Segmentation

3Productivity

If hardware components are implemented in ASIC memory, then processing efficiency is improved, but device complexity increases

Engineering Contradiction:

Improveprocessing efficiencyVSAvoidhardware complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple protocol stack processing functions into a single integrated ASIC memory component. The MAC layer core, stream layer core, decryption layer core, defragmentation layer core, and sync layer core are all implemented as hardware modules within the same ASIC memory, consolidating what would otherwise be separate hardware components into one unified device. This merging approach improves processing efficiency through hardware acceleration while minimizing the increase in device complexity by integrating functions rather than adding separate components.

Inventive Principle:

Principle #5Merging (Combining)

4Quantity of substance

If data is processed in place in ASIC memory, then memory usage is reduced, but data transfer overhead increases

Engineering Contradiction:

Improvememory usageVSAvoiddata transfer overhead

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The patent implements self-service processing where the ASIC memory component performs all protocol stack operations (deinterleaving, Reed-Solomon decoding, decryption, defragmentation, and sync header parsing) directly within its own memory structure. The hardware cores process data in place without requiring transfer to external host processor memory, enabling the ASIC memory to serve its own processing needs and eliminating the data transfer overhead that would otherwise occur between separate memory systems.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS7782903B2Hardware accelerated protocol stack

Publication Date: 2010.08.24 ATMEL CORP

AI summary

Protocol stack layer processing for a MediaFLO™ mobile multimedia multicast system comprising a transmitter comprising a host processor and a host memory component. The processing includes a receiver that receives a wireless data stream comprising a MediaFLO™ mobile multimedia multicast system superframe comprising any of audio, video, and text media frames arranged in multiplexed Multicast Logical Channels (MLCs) and received from the transmitter, wherein each MLC is divided into 16 byte data packets, and wherein each MLC carries up to three logical sub-channels comprising stream 2, stream 1, and stream 0; and an Application Specific Integrated Circuit (ASIC) memory component operatively connected to the receiver, wherein the ASIC memory component performs processing of the data packets using hardware components comprising, a Medium Access Control (MAC) layer core; a stream layer core; a decryption layer core; a defragmentation layer core; and a sync layer core.