ASIC IIR RF Filtering to Cut FPGA Power Dissipation
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Solution Overview
Problem
Existing RF signal processing systems face challenges with nonlinear distortion, external interference, and high Size Weight and Power (SWaP) requirements due to the use of Field Programmable Gate Arrays (FPGAs) for filtering and processing, which increase complexity and power dissipation.
Innovation Solution
Implementing an RF device with an application-specific integrated circuit (ASIC) that includes ADCs, DSP cores, complex coefficient multipliers, band pass filters, and DACs, along with a feedback loop and a processor for controlling these components, allowing for flexible and efficient digital filtering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Field Programmable Gate Array (FPGA) circuits are used for filtering and processing, then flexibility and adaptability are improved, but power dissipation and device complexity increase
Solution Approach 1:
The FPGA filter circuit is segmented into multiple functional blocks including multiple ADCs, multiple DSP cores, multiple DACs, and supporting circuits. Each segment performs a specific function in the signal processing chain, allowing independent optimization and reducing overall power consumption while maintaining flexibility.
Solution Approach 2:
The system employs dynamic resource allocation where the processor selectively enables or disables specific ADCs, DSP cores, and DACs based on current processing requirements. This dynamic activation/deactivation of components optimizes power consumption while maintaining adaptability for different signal processing tasks.
2Adaptability or versatility
If Field Programmable Gate Array (FPGA) circuits are used for filtering and processing, then flexibility and adaptability are improved, but device complexity and cost increase
Solution Approach 1:
The complex FPGA filter is divided into modular functional blocks (multiple ADCs, DSP cores, DACs, feedback loops) that can be independently configured and managed. This segmentation reduces overall system complexity by allowing each module to be optimized separately while maintaining overall flexibility.
Solution Approach 2:
The processor serves multiple functions by selectively controlling different combinations of ADCs, DSP cores, and DACs based on processing requirements. This multi-functionality reduces the need for dedicated hardware for each function, thereby reducing device complexity while maintaining adaptability.
3Productivity
If multiple ADCs and DSP cores are implemented in the ASIC, then processing capability and flexibility are improved, but manufacturing complexity increases
Solution Approach 1:
The ASIC is designed with segmented functional modules including multiple ADCs, multiple DSP cores, and supporting circuits. Each module is designed independently with standardized interfaces, facilitating modular manufacturing and assembly while enabling high processing capability through parallel operation of multiple cores.
Solution Approach 2:
Multiple functional components (ADCs, DSP cores, DACs, feedback loops) are merged into a single integrated ASIC chip rather than being implemented as separate discrete components. This integration reduces manufacturing complexity by consolidating multiple functions into one device while maintaining high processing capability.
Data Source
AI summary
An RF device may include an RF antenna, and an ASIC downstream from the RF antenna. The ASIC may include ADCs configured to generate replica digitized input signals, a DSP core downstream from the ADCs and having first complex coefficient multipliers, first band pass filters respectively coupled to the first complex coefficient multipliers, and a summer downstream from the first band pass filters. The ASIC may also include DACs configured to generate analog output signals, and a feedback loop coupled between the DACs and the ADCs. The RF device may further include a processor configured to control the first complex coefficient multipliers and associated delay circuits.