Staggered Power-Up for Large ASICs to Manage Current Transients
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Large current transients during power-up in high gate count ASICs and FPGAs pose a challenge for power systems, leading to potential device damage and operational issues due to sudden current changes that exceed the capabilities of typical power supplies.
Innovation Solution
Implementing a method to enable a gradual power-up by selectively enabling the system clock independently to each block within the ASIC or FPGA, allowing current changes to be discretized into small increments, and using software control to manage these changes, ensuring that multiple blocks emerge from reset on a common clock edge without requiring additional components or larger power systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all blocks are enabled simultaneously during power-up, then the device can start operating quickly, but large current transients occur that exceed power system capabilities
Solution Approach 1:
The patent divides the chip into multiple independent blocks, each with its own clock enable signal. During power-up, these blocks are enabled sequentially rather than simultaneously, breaking the large current transient into smaller manageable segments that the power system can handle.
Solution Approach 2:
The patent implements preliminary staging of block enablement where blocks are prepared in stages before full operation. Software control预先 configures which blocks should be enabled first, allowing the power system to gradually accommodate increasing current demands rather than facing a sudden large transient.
2Power
If blocks are enabled gradually to reduce current transients, then power system stress is reduced, but blocks may become desynchronized and fail to operate properly
Solution Approach 1:
The patent introduces a global reset signal as an intermediary mechanism that overrides the staggered clock enablement. This reset signal ensures all blocks are held in a known state until synchronization is achieved, then releases them simultaneously on a common clock edge, guaranteeing proper synchronization regardless of their enablement sequence.
Solution Approach 2:
The patent changes the operational parameter of blocks from asynchronous independent operation to synchronous operation on a common clock edge. By controlling clock enablement and using a global reset mechanism, all blocks transition to the same operational state at the same time, ensuring synchronization while maintaining gradual power-up benefits.
3Reliability
If reset signals are distributed across a large die, then all blocks can be reset, but signal propagation latency causes timing constraints and layout difficulties
Solution Approach 1:
The patent makes the reset signal dynamic by tying its de-assertion to the clock signal itself. Rather than using a static or separately controlled reset signal that must propagate across the entire die, the reset is automatically synchronized to clock edges, allowing flexible layout without strict timing constraints on reset signal propagation.
Data Source
AI summary
Methods and apparatus for controlling the power-on current transients and for providing a gradual current draw in an ASIC or FPGA having a high gate count and a number of physical blocks are disclosed. Additionally, method(s) are disclosed which ensure related blocks emerge from a reset state on a common clock cycle even when the related blocks are geographically dispersed over a large area producing multiple clock cycle latency periods for signals between blocks. Complete flexibility of physical block start up is achieved by software control which permits the sequence and number of physical blocks started simultaneously.