ASIC Instruction Rate Throttling for Overcurrent Power Limits
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Solution Overview
Problem
The rapid evolution of machine learning applications necessitates short design and manufacturing cycles for ASICs, leading to potential overheating and damage due to power exceeding system capacity, resulting in shutdowns and loss of computation.
Innovation Solution
An integrated circuit die with a voltage regulator that measures current load, detects overcurrent conditions, and sends signals to throttle processing rates using a throttling mask, synchronized with the IC die's internal clock to manage power usage and prevent overheating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the ASIC operates at high processing rates to meet evolving machine learning application demands, then productivity is improved, but power consumption exceeds system capacity causing overheating and shutdowns
Solution Approach 1:
The patent implements dynamic power management by making the ASIC's processing rate adjustable in real-time. The system transitions from a static fixed processing rate to a dynamic rate that adapts to power availability, allowing the device to operate at high speeds when power is sufficient and reduce speed when power limits are approached, thus resolving the contradiction between productivity and power consumption
Solution Approach 2:
The patent changes the operational parameters of the ASIC by introducing variable processing rates. Instead of operating at a single fixed rate, the system modifies the processing rate parameter dynamically based on power conditions, enabling the ASIC to optimize between productivity and power consumption by adjusting this key operational parameter in response to system feedback
2Reliability
If the power supply shuts down the ASIC when power limits are exceeded, then reliability is improved by preventing damage, but productivity is lost due to shutdowns and computation loss
Solution Approach 1:
The patent applies preliminary action by proactively reducing the processing rate before power limits are exceeded. Instead of waiting for shutdown conditions to occur, the system monitors power consumption and preemptively throttles the processing rate to stay within safe power boundaries, thus maintaining both reliability and continuous productivity without actual shutdowns
Solution Approach 2:
The patent implements a feedback mechanism where the system continuously monitors power consumption and uses this information to adjust the processing rate. This closed-loop control allows the ASIC to respond to actual power conditions in real-time, maintaining reliable operation within power limits while maximizing computational output by avoiding unnecessary shutdowns
3Use of energy by moving object
If the ASIC processing rate is reduced to stay within power limits, then power consumption is controlled, but productivity decreases due to slower processing
Solution Approach 1:
The patent resolves this contradiction through dynamic rate adjustment, allowing the ASIC to operate at high processing rates when power is abundant and automatically reduce the rate only when necessary to stay within power limits. This dynamic approach ensures that productivity is maximized during favorable conditions while power consumption is controlled during constrained conditions, rather than operating at a consistently reduced rate
Data Source
AI summary
A system contains a machine learning application specific integrated circuit (ASIC) and a power supply unit. The power supply unit and the ASIC are configured to be in data communication through dedicated pins on the ASIC and the power supply unit. The power supply unit detects a present power consumption of the ASIC. Upon determining that a threshold condition has been met, the power supply unit, responsive to the condition sends a digital signal to the ASIC. The ASIC contains a synchronizer which synchronizes the digital signal to be consistent with the ASICs internal clock frequency. A chip manager the synchronized signal and other signals to generate a throttling mask. The throttling mask is sent to a sequencer of the ASIC, which then limits the instruction flow into the processing units of the ASIC based on the mask. This in turn limits the power being consumed by the ASIC.