ASIC Tile Scheduling With Delay Registers for Power-Limited Throughput
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Solution Overview
Problem
Existing neural network systems face challenges in maintaining power consumption and current rate within design constraints, especially during high computational loads or potential attacks, as concurrent activation of all tiles can exceed these limits.
Innovation Solution
The integrated circuit can operate in two modes: a first mode where all tiles receive input data simultaneously and a second mode where a delay is introduced in the operation of a subset of tiles, staggering data processing to prevent exceeding power and current constraints, achieved by using an array of tiles with delay registers and a controller to dynamically select the mode based on the number or percentage of operable tiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all tiles receive input data simultaneously (concurrent mode), then computational productivity is improved, but power consumption and current rate exceed design constraints
Solution Approach 1:
The system dynamically switches between two operational modes based on computational load: concurrent mode for high throughput when power constraints are not violated, and staggered mode when power consumption exceeds thresholds. This dynamic adaptation resolves the contradiction by adjusting operational characteristics in real-time rather than being fixed in one mode.
Solution Approach 2:
The staggered mode introduces periodic timing delays between groups of tiles, creating a rhythmic pattern of activation that spreads power consumption over time. This periodic action prevents simultaneous peak draws from all tiles, maintaining computational progress while respecting power constraints.
2Speed
If all tiles operate concurrently, then processing speed is improved, but the integrated circuit becomes vulnerable to attacks exceeding current rate constraints
Solution Approach 1:
The system proactively introduces staggered timing delays as a preventive measure against attacks that could exploit concurrent operation. By deliberately creating temporal separation in tile activation, the system neutralizes potential attack vectors before they can exploit simultaneous high-current operation, while still maintaining acceptable processing throughput.
3Use of energy by moving object
If staggered mode is used to reduce power consumption, then power constraints are satisfied, but computational productivity decreases
Solution Approach 1:
The system dynamically selects between staggered and concurrent modes based on real-time assessment of computational load and power constraints. When workloads are moderate, staggered mode maintains power compliance. When workloads justify higher throughput and power budgets allow, concurrent mode maximizes productivity. This dynamic selection resolves the contradiction by optimizing the trade-off contextually rather than statically.
Data Source
AI summary
A method for operating an integrated circuit chip including multiple tiles (202a-202d) includes determining a configuration for the tiles for execution of a computation. When the configuration for the tiles satisfies a first criterion, the integrated circuit is operated in a first mode, including concurrently receiving respective input data (208a, 208b) at each of the tiles (202a-202d). When the configuration for the tiles satisfies a second criterion, the integrated circuit is operated in a second mode, including: at a first time, concurrently receiving respective first input data (208a, 208b) at each tile (202a, 202b) of a first group of tiles; at the first time, storing respective second input data (208a, 208b) in each of multiple delay registers (212a, 212b), each delay register corresponding to a tile (202c, 202d) of a second group of tiles; at a second time, releasing the second input data from the delay registers (212a, 212b) and receiving the released respective second input data at each tile (202c, 202d) of the second group of tiles.