ASIC Timing Constraint Verification via Attribute-Point Comparison
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Solution Overview
Problem
Design porting of integrated circuits across different technology nodes faces challenges in ensuring that timing constraints are accurately verified and maintained, leading to potential mismatches and the need for extensive redesigns due to incomplete pin-to-pin compatibility and re-partitioning of circuit designs.
Innovation Solution
An attribute-point-based timing constraint formal verification methodology is employed to identify and correct mismatches in timing constraints by comparing critical attributes point-by-point between a golden and target circuit design, using static timing analysis databases to ensure functional equivalence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If design porting is performed across technology nodes, then design time is reduced through re-use of circuit blocks, but timing constraint verification becomes challenging due to incomplete pin-to-pin compatibility and re-partitioning
Solution Approach 1:
The patent replaces manual timing constraint verification with automated formal verification using attribute-point-based comparison. The system automatically extracts timing attributes from both the original and ported designs, compares them systematically, and identifies mismatches without human intervention, thereby maintaining reliability while supporting design porting efficiency
Solution Approach 2:
The patent creates a formal representation (copy) of timing constraints from the original design and compares it with the ported design's timing attributes. This copying approach allows systematic verification of timing constraints across technology nodes, ensuring that the ported design maintains temporal equivalence with the original design
2Reliability
If traditional timing verification methods are used, then comprehensive checking can be performed, but the process is time-consuming and requires extensive manual effort
Solution Approach 1:
The patent segments the timing verification process into distinct attribute categories (arrival time, departure time, clock skew, etc.) and verifies each attribute independently through systematic point-by-point comparison. This segmentation enables automated processing of complex timing constraints while maintaining comprehensive verification coverage
Solution Approach 2:
The patent implements self-service verification where the system automatically extracts, compares, and reports timing attribute mismatches without requiring manual analysis. The formal verification process autonomously identifies issues in the ported design, eliminating the need for time-consuming manual verification efforts
3Loss of time
If attribute-point-based formal verification is implemented, then mismatches are quickly identified and design iteration time is reduced, but hardware usage increases due to additional verification infrastructure
Solution Approach 1:
The patent replaces hardware-intensive manual verification processes with software-based formal verification. The attribute-point-based comparison is performed through automated tools that analyze timing attributes computationally, significantly reducing design iteration time while minimizing additional hardware requirements compared to physical prototyping approaches
Data Source
AI summary
Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA). The attribute mismatch is provided for further design or timing constraint modifications and/or updates using this approach, particularly timing formal verification, at the target technology in order to enable efficient design timing sign-off based on ported netlists and synthesis design constraints (SDC).