ASIC VXLAN Header Processing for Faster Packet Encapsulation
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Solution Overview
Problem
Current methods for processing VXLAN packets are inefficient due to software limitations and the difficulty in performing uniform operations on packets using hardware, particularly in handling VXLAN headers for upstream and downstream packets.
Innovation Solution
Utilizing hardware, specifically an Application Specific Integrated Circuit (ASIC), to accelerate the generation, removal, and modification of VXLAN packets by determining packet types and applying prototype headers or removing VXLAN headers based on predefined tables and look-up mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software is used to parse and convert packet formats for VXLAN, then VXLAN functionality can be implemented, but processing speed is insufficient
Solution Approach 1:
The patent replaces software-based packet parsing and conversion with hardware-based processing. Specifically, it uses a combination of lookup tables stored in memory and hardware logic circuits to perform VXLAN header removal, addition, and modification operations directly in hardware, eliminating the need for software intervention and thereby achieving high-speed processing.
Solution Approach 2:
The patent pre-stores VXLAN header information, including various header formats and conversion rules, in lookup tables within the hardware. This preliminary preparation allows the hardware to quickly retrieve and apply the appropriate VXLAN processing rules during packet forwarding without real-time computation, significantly improving processing speed.
2Productivity
If hardware is used to process VXLAN packets, then processing speed improves, but it is difficult to perform uniform operations on all packet types
Solution Approach 1:
The patent designs a universal hardware processing architecture that can handle multiple packet types and VXLAN header formats through a single unified approach. The system uses lookup tables to store different VXLAN header configurations and uses hardware logic to automatically select and apply the appropriate processing rules based on packet characteristics, enabling one hardware structure to perform multiple VXLAN operations (header removal, addition, modification) on various packet types.
Solution Approach 2:
The patent achieves adaptability to different packet types by changing parameters stored in lookup tables rather than changing the hardware structure. The lookup tables contain configurable parameters such as VXLAN header formats, VNI values, and processing rules that can be dynamically updated to match different packet types and network requirements, allowing the same hardware to adapt to various scenarios.
3Productivity
If VXLAN headers are removed and added for different packets in hardware, then processing speed improves, but the difficulty of implementing uniform hardware operations increases
Solution Approach 1:
The patent segments the VXLAN header processing into distinct functional modules within the hardware: a VXLAN header removal module, a VXLAN header addition module, and a header modification module. Each module is responsible for a specific operation and can be independently controlled through lookup tables. This segmentation allows the hardware to handle different VXLAN operations through standardized, modular processes rather than requiring complex unified logic.
Data Source
AI summary
A method for accelerating the generation of Virtual Extensible Local Area Network (VXLAN) packets with an application specific integrated circuit (ASIC) includes the following steps: determining whether an original packet is an upstream packet; when the original packet is the upstream packet, determining whether the original packet is for a VXLAN egress interface; when the original packet is for the VXLAN egress interface, adding a prototype outer header to the front of the original packet and thereby generating a VXLAN packet; and after generating the VXLAN packet, determining whether to modify the content of the prototype outer header.