Compiler Generation for ASIPs Using Directed Acyclic Graph Scheduling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current techniques for generating compilers for architecture exploration loops in embedded processor design are inefficient and limited in their ability to handle complex architectures, particularly for ASIPs, due to lengthy and complex constraint lists and restricted architecture compatibility.
Innovation Solution
A method and system that automatically extract information from an architecture description to construct a directed acyclic graph, maintain ready and not scheduled lists, and determine the next instruction to schedule, enabling efficient and accurate compiler generation compatible with existing technologies for embedded processors and ASIPs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional compiler generation techniques are used for architecture exploration, then the process is limited to specific architecture types, but the device complexity and architecture compatibility are reduced
Solution Approach 1:
The patent creates a universal compiler framework that can generate compilers for multiple architecture types (VLIW, DSP, RISC, CISC) using a single architecture description language (IDA). The system uses parameterized processor models and unified instruction set descriptions that can be configured for different target architectures, eliminating the need for separate compiler generation processes for each architecture type.
Solution Approach 2:
The system employs parameterized processor models where architecture-specific characteristics (pipeline stages, functional units, register files, memory hierarchies) are defined as configurable parameters in the IDA language. By changing these parameters, the same compiler generation framework can adapt to different architecture types without fundamental redesign.
2Manufacturing precision
If detailed constraint lists are used to describe architecture limitations, then the manufacturing precision of compiler generation is improved, but the device complexity and constraint list length increase
Solution Approach 1:
The patent extracts architecture constraints directly from the processor model definition in the IDA language rather than maintaining separate constraint lists. The compiler generation process automatically derives constraints (resource availability, timing requirements, instruction format limitations) from the parametric processor description, eliminating the need for manual constraint specification.
Solution Approach 2:
The system implements automatic validation and constraint checking where the compiler generator continuously verifies generated code against the processor model constraints. The framework provides feedback loops that detect constraint violations and trigger automatic corrections or error reporting, ensuring compiler generation accuracy without manual constraint management.
3Productivity
If manual processor resource specification is used, then the ease of operation is improved for simple architectures, but the productivity and design exploration time decrease for complex architectures
Solution Approach 1:
The patent provides pre-defined processor model templates and instruction set libraries in the IDA language that capture common architecture patterns (VLIW, DSP, RISC). These templates include pre-configured functional units, pipeline stages, and resource definitions that can be instantiated and modified for specific architectures, eliminating the need to build processor models from scratch.
Solution Approach 2:
The processor model is segmented into modular components (pipeline stages, functional units, register files, memory hierarchies) that can be independently defined and configured in the IDA language. Each component has a standardized interface and can be combined to form complete processor models, making the description process more manageable and less error-prone.
Data Source
AI summary
A method of automatically extracting information from an architecture description. A memory resident directed acyclic graph data structure comprising nodes representing instructions and edges whose weights represent dependencies between pairs of instructions is constructed. A list of ready nodes are maintained in the directed acyclic graph. A list of nodes not scheduled is maintained. And, it is determined whether the next instruction to be scheduled is to be taken from the list of ready nodes or from the list of nodes not yet scheduled.