ASIP with Custom Functional Units for Multi-Standard Signal Processing
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Solution Overview
Problem
Current digital radio processors face challenges in supporting multiple wireless standards like GSM, GPRS, EDGE, and WCDMA due to their fixed-logic architecture, which lacks configurability and flexibility, making it difficult to meet varying data rate requirements without significant architectural changes or increased area overhead.
Innovation Solution
An application-specific instruction set processor (ASIP) with custom functional units and instructions is introduced, allowing for reconfigurable signal processing by tightly coupling these units with the processor core, enabling efficient execution of FDRX operations across different standards, including 16-bit GGE and 8-bit/16-bit WCDMA modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed-logic architecture is used for FDRX blocks, then manufacturing precision and reliability are improved, but adaptability and flexibility deteriorate
Solution Approach 1:
The patent applies dynamics by transforming the static fixed-logic architecture into a dynamic reconfigurable architecture. The FDRX blocks are implemented using programmable logic elements that can be dynamically configured through instruction sets to support different wireless standards (GSM, WCDMA, etc.) and data rates, while maintaining reliable operation through structured control mechanisms
Solution Approach 2:
The patent changes the configurability parameter of the FDRX blocks by introducing programmable logic with instruction sets. This allows the same hardware blocks to be reconfigured for different standards and data rates by loading appropriate instruction sequences, thereby achieving adaptability without sacrificing manufacturing precision
2Adaptability or versatility
If multiple dedicated data paths are employed to cover different standards, then adaptability is improved, but device complexity and area increase
Solution Approach 1:
The patent implements universality by designing a single reconfigurable FDRX data path that can perform multiple functions for different wireless standards. Through programmable logic and instruction sets, the same hardware blocks (FIR filters, IIR filters, decimators) can be configured to handle GSM, WCDMA, and other standards, eliminating the need for multiple dedicated data paths and reducing overall device complexity
3Productivity
If clock frequency is increased to meet higher data rates, then productivity is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent applies dynamics by introducing reconfigurable logic that can be programmed for different data rates without changing the physical clock frequency. The same hardware blocks can be configured to operate at different effective data rates through instruction-based control, avoiding the need to increase clock frequency and the associated complexity and power consumption
Data Source
AI summary
This invention is an application specific integrated processor to implement the complete fixed-rate DRX signal processing paths (FDRX) for a reconfigurable processor-based multi-mode 3G wireless application. This architecture is based on the baseline 16-bit RISC architecture with addition functional blocks (ADU) tightly coupled with the based processor's data path. Each ADU accelerates a computation-intensive tasks in FDRX signal path, such as multi-tap FIRs, IIRs, complex domain and vectored data processing. The ADUs are controlled through custom instructions based on the load/store architecture. The whole FDRX data path can be easily implemented by the software employing these custom instructions.