Reconfigurable ASIP PLL Circuitry for Multi-Standard RF Spur Reduction
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Solution Overview
Problem
Conventional all digital phase locked loop (ADPLL) circuits are inflexible and difficult to reconfigure, making them unsuitable for multi-standard wireless applications, and they generate significant current transients that result in unwanted RF spurs in sensitive frequency bands.
Innovation Solution
A software-based ADPLL architecture with a reconfigurable calculation unit (RCU) that can perform all phase locked loop operations within a single reference clock cycle, using an application-specific instruction-set processor (ASIP) to optimize computations and reduce silicon area and RF spurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a hardwired circuit design is used for ADPLL, then the circuit operates at lower speed with dedicated hardware, but the design lacks reconfigurability and requires months of delay for any modification
Solution Approach 1:
The patent implements a reconfigurable calculation unit (RCU) that can dynamically change its operation mode through software control. The RCU can be configured to perform different atomic operations (addition, subtraction, shifting, latching) by changing control signals, allowing the ADPLL to adapt to different wireless standards without physical redesign. This dynamic reconfigurability resolves the contradiction by enabling versatility while maintaining a fixed hardware structure.
Solution Approach 2:
The RCU is designed as a universal computing unit that can perform multiple functions (arithmetic operations, logical operations, data storage) within a single circuit block. By using a general-purpose computational unit instead of dedicated hardware for each function, the design achieves multi-standard support while reducing overall design complexity. The same RCU hardware serves different purposes under different software configurations.
2Object-affected harmful factors
If conventional ADPLL circuits are used, then the circuit structure is fixed, but they generate significant current transients that result in unwanted RF spurs
Solution Approach 1:
The patent implements a non-uniform clocking scheme where the RCU operates at different clock frequencies depending on the operational phase. During critical phases where current transients would generate RF spurs, the clock frequency is reduced or gated off. This periodic modulation of the operating frequency reduces harmful current transients while maintaining operational flexibility through software-controlled timing.
Solution Approach 2:
The patent converts the harmful effect of current transients into a beneficial timing mechanism by deliberately introducing controlled idle cycles or low-activity periods. These periods, which could be seen as reducing productivity, actually serve to minimize RF spur generation by reducing switching activity during sensitive time windows, while the overall system remains flexible through software coordination.
3Speed
If a microprocessor based implementation is used, then shared hardware runs at higher speed, but the hardware area increases compared to hardwired implementation
Solution Approach 1:
The patent merges multiple dedicated hardware functions into a single reconfigurable calculation unit. Instead of having separate hardware blocks for addition, subtraction, shifting, and latching operations, the RCU combines these functions into one unified computational unit. This consolidation reduces the total silicon area while maintaining high operating speed, as the RCU can sequentially perform different operations at microprocessor speeds.
Data Source
AI summary
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.