ASIP Architecture With Separated Input Output Data Ports
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Solution Overview
Problem
Traditional processors have multiplexed input and output data ports on the same bus lines, leading to lower performance and throughput due to the need for separate address mapping, resulting in longer instruction code words and inefficient resource usage.
Innovation Solution
An Application Specific Instruction-Set Processor (ASIP) design with separate input and output data ports on distinct bus lines, utilizing a Very Long Instruction Word (VLIW) that allows simultaneous execution of atomic application-specific instructions, sharing the same address mapping for input and output operations, thereby reducing the number of bits required for address indication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate input and output data ports are used, then processor performance and throughput are improved, but the number of bits for address mapping increases
Solution Approach 1:
The patent combines the address spaces of input and output data ports by using the same address mapping for both. This allows the processor to access input and output ports through a unified addressing scheme, reducing the number of address bits required while maintaining separate physical data paths for input and output operations
2Productivity
If separate input and output data ports are used, then processor performance is improved, but instruction code word length increases
Solution Approach 1:
By merging the address spaces of input and output ports into a single unified address map, the patent reduces the number of bits needed to specify port addresses in instruction code words. This allows shorter instruction formats while still supporting separate input and output data paths, thereby improving performance without proportionally increasing instruction length
3Device complexity
If multiplexed data ports are used, then address mapping is simplified, but resource usage efficiency decreases
Solution Approach 1:
The patent segments the data I/O functionality into separate input data ports and output data ports that operate on distinct bus lines. This segmentation allows simultaneous read and write operations without multiplexing conflicts, improving resource utilization efficiency while using a unified address mapping scheme to access both types of ports
Data Source
AI summary
The invention provide an application specific instruction-set processor (ASIP) that uses a Very Long Instruction Word (VLIW) for executing atomic application specific instructions. The ASIP includes one or more units for executing a first set of atomic application specific instructions for receiving a first set of data across a plurality of input data ports in a first operation specified in an instruction word. Further, the one or more units execute a second set of atomic application specific instructions for outputting a second set of data across a plurality of output data ports in a second operation specified in the instruction word, wherein an input data port of the plurality of input data ports and a corresponding output data port of the plurality of output data ports share a same address location and are specified as operands in the instruction word. Thus, the first operation and the second operation can occur simultaneously.