Ultra Low Power ASIP Architecture Wide Register Design
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Solution Overview
Problem
Current microcomputer architectures face significant challenges in reducing power consumption, particularly in biomedical applications where sustained battery-less operation is required, with existing technologies failing to achieve the necessary energy efficiency to support complex signal processing and data transmission within the scavenging energy limit of 50 μW, leading to high energy bottlenecks in the instruction memory hierarchy and register file.
Innovation Solution
The proposed microcomputer architecture incorporates a wide register design where multiple second memory units are simultaneously accessible by both the first memory unit and the functional unit, allowing for bidirectional access without simultaneous reading and writing, and utilizes a single-ported register configuration to reduce energy consumption, along with a memory management unit and data shifter for efficient data processing and routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional VLIW-DSP architecture is used to provide algorithmic flexibility and programmability, then the system can execute complex biomedical algorithms, but the power consumption exceeds the scavenging energy limit of 50 μW
Solution Approach 1:
The processor architecture is segmented into distinct functional units (FUs) with specialized purposes. Each FU handles specific operations, allowing the system to execute complex algorithms while minimizing the activation of unused units, thereby reducing overall power consumption while maintaining algorithmic flexibility.
Solution Approach 2:
The architecture employs dynamic power management where functional units are selectively activated based on the computational requirements of the executed algorithm. This dynamic activation approach allows the system to adapt its power consumption to the actual computational load, maintaining versatility while staying within energy constraints.
2Productivity
If the register file is designed with multiple ports for simultaneous access by memory and functional units, then data processing efficiency is improved, but the power consumption of the register file increases significantly
Solution Approach 1:
The register file uses periodic action through clock-gating techniques where clock signals are selectively enabled only when data transfer operations are required. This allows the register file to maintain its multi-port architecture for efficient data processing while reducing power consumption by disabling clocking to inactive ports during idle periods.
Solution Approach 2:
Different regions or ports of the register file are configured with different operational characteristics based on their usage patterns. Frequently accessed ports maintain full performance while less active ports are optimized for lower power consumption, achieving a balance between data processing efficiency and power usage.
3Measurement precision
If data is frequently transferred between memory and register file to support complex signal processing, then computational accuracy is maintained, but the energy bottleneck in the memory hierarchy is exacerbated
Solution Approach 1:
The architecture pre-loads frequently accessed data into the register file before it is needed by functional units. This preliminary action reduces the frequency of memory-to-register transfers during actual computation, maintaining computational accuracy while significantly reducing the energy bottleneck in the memory hierarchy.
Solution Approach 2:
The system maintains continuous useful action by keeping relevant data in the register file throughout the computation process, eliminating unnecessary memory access cycles. This continuity ensures computational accuracy is maintained while minimizing energy loss in the memory hierarchy by reducing transfer operations.
Data Source
AI summary
A microcomputer architecture comprises a microprocessor unit and a first memory unit, the microprocessor unit comprising a functional unit and at least one data register, the functional unit and the at least one data register being linked to a data bus internal to the microprocessor unit. The data register is a wide register comprising a plurality of second memory units which are capable to each contain one word. The wide register is adapted so that the second memory units are simultaneously accessible by the first memory unit, and so that at least part of the second memory units are separately accessible by the functional unit.