ASK Demodulator Peak Sampling With Frequency Lock Continuity
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Solution Overview
Problem
Conventional amplitude demodulators suffer from distortion, non-linear effects, and high power consumption, limiting their usability and accuracy in wireless communication systems like NFC and RFID.
Innovation Solution
The development of an amplitude demodulator comprising a clock extractor, phase shifter, sampler, and voltage-controlled locking oscillator, which extracts a clock signal, phase-shifts it by π/2, and continues sampling even when the input signal amplitude is zero, using a voltage-controlled locking oscillator to maintain frequency lock and reduce distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional amplitude demodulators are used, then demodulation function is provided, but distortion and non-linear effects occur
Solution Approach 1:
The patent replaces conventional mechanical/envelope demodulation methods with a sampling-based digital approach. A sampler captures the amplitude-modulated signal at specific instants determined by a clock signal, and an analog-to-digital converter transforms the sampled signal into digital form for processing. This substitution eliminates the non-linear distortion inherent in traditional envelope detection while preserving the demodulation function.
2Power
If conventional amplitude demodulators are used, then demodulation is achieved, but power consumption is high
Solution Approach 1:
The patent extracts only the essential information from the amplitude-modulated signal by sampling at specific instants rather than continuously processing the entire signal. The sampler captures amplitude information at discrete time points determined by the clock signal, and the analog-to-digital converter processes only these sampled points. This extraction approach significantly reduces power consumption compared to continuous processing while maintaining demodulation reliability.
3Device complexity
If sampling is performed without frequency locking, then circuit complexity is reduced, but sampling continuity fails when signal amplitude is zero
Solution Approach 1:
The patent introduces a voltage-controlled locking oscillator as an intermediary component that generates a clock signal synchronized to the frequency of the amplitude-modulated signal. This oscillator acts as a mediator between the input signal and the sampler, ensuring that sampling continues even when the signal amplitude becomes zero. The oscillator maintains frequency lock and provides continuous sampling timing without adding significant circuit complexity.
Data Source
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AI summary
A circuit for demodulating an input signal is described. The circuit may be configured to demodulate signals modulated with amplitude-based modulation schemes, such as amplitude shift keying (ASK). The demodulator may comprise a clock extractor configured to generate a clock signal in response to receiving an amplitude-modulated input signal, a phase shifter configured to generate a sampling signal by phase-shifting the clock signal by approximately π/2, and a sampler configured to sample the input signal in correspondence to one or more edges (such as one or more falling edges) of the sampling signal. In this way, the amplitude-modulated input signal may be sampled at its peak, or at least near its peak, thus ensuring high signal fidelity.