Automatic Soft Post-Package Repair Logic for DRAM
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently performing fast and specific temporary repairs of word lines, particularly in dynamic random access memory (DRAM), where defective rows need rapid identification and redirection to redundant rows, especially after packaging, and current soft post-package repair (SPPR) operations are slow due to reliance on fuse logic scans.
Innovation Solution
The implementation of automatic soft post-package repair (ASPPR) logic, which uses a controller to monitor memory for bad pages, provides a row address and bad page command through existing communication architecture, saving the physical address in ASPPR registers, allowing for rapid and automatic capture of the physical address, even if the logical to physical address mapping changes, thereby enabling faster repair operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional fuse logic scans are used for soft post-package repair, then repair operations can be performed, but the repair process becomes slow and time-consuming
Solution Approach 1:
The patent performs preliminary action by capturing and storing the physical address of the defective word line during normal memory operations before the repair is needed. The ASPPR register saves the physical address immediately when a bad page is detected, so that when repair is required, the address is already available without needing to scan through fuse logic or perform time-consuming address translation.
Solution Approach 2:
The patent introduces an intermediary mechanism - the ASPPR register - that acts as a mediator between the memory controller and the repair process. This register temporarily stores the physical address information, allowing the system to bypass the slow fuse logic scan process and directly access the needed address information for repair operations.
2Ease of repair
If the memory device performs repair operations row-by-row with address redirection, then defective rows can be repaired, but the process becomes complex and difficult to implement after packaging
Solution Approach 1:
The patent implements self-service by allowing the memory device to automatically detect bad pages, capture the physical address, and prepare repair information without external intervention. The ASPPR mechanism operates autonomously within the memory device, using its own internal resources (registers, command/address bus) to perform the repair preparation, eliminating the need for complex external testing equipment or manual address remapping processes.
Solution Approach 2:
The patent extracts the essential repair information (physical address) from the complex address remapping process and isolates it in the ASPPR register. This separation allows the repair function to operate independently from the complex address translation logic, simplifying the overall implementation by removing only the necessary information while leaving the complex remapping mechanisms in place.
3Speed
If the memory uses normal command/address bus operations for repair, then repair speed increases, but the existing communication architecture must be utilized efficiently
Solution Approach 1:
The patent applies universality by making the command/address bus serve multiple functions: normal memory operations and repair operations. The same bus that is used for routine read/write operations is also utilized for capturing and transmitting the physical address during repair processes, eliminating the need for separate dedicated repair communication channels and avoiding additional hardware complexity.
Solution Approach 2:
The patent merges the repair operation functions into the existing command/address bus architecture. By combining the address capture, storage, and transmission functions with the normal memory access pathway, the system achieves fast repair operations without adding separate hardware infrastructure, effectively merging repair capabilities with the existing communication architecture.
Data Source
AI summary
Embodiments of the disclosure are drawn to apparatuses and methods for automatic soft post-package repair (ASPPR). A memory may receive a row address along with a signal indicating an ASPPR operation, such as a bad page flag being set. A word line engine generates a physical address based on the row address, and ASPPR registers stores the physical address. The time it takes from receiving the row address to storing the physical address may be within the timing of an access operation on the memory such as tRAS. The row address may specify a single page of information. If the bad page flag is set, then a subsequent PPR operation may blow fuses to encode the physical address stored in the ASPPR registers.