Assembly Instruction Sequence Generation for Multi-Core Memory Contention
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Solution Overview
Problem
Current methods for generating sequences of assembly language instructions are time-consuming and require manual expertise, limiting sequence size and diversity, and struggle to produce instructions with varied and precisely chosen characteristics for memory contention analysis, especially in multi-core processors, making it difficult to anticipate and quantify memory interference.
Innovation Solution
An automated method for generating sequences of assembly language instructions that includes selecting instructions based on statistical metrics and rules to achieve specific memory access profiles, ensuring error-free execution and varied characteristics, allowing for the rapid creation of large sequences with controlled memory contention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual construction of assembly code sequences is performed by a programmer, then execution correctness and compliance with constraints are ensured, but time consumption increases significantly and sequence size is limited
Solution Approach 1:
The system performs self-service through automated generation of assembly code sequences using a Markov chain model. The generator automatically creates sequences with specified characteristics (memory access patterns, instruction types) without requiring manual programming, thereby reducing time consumption while maintaining execution correctness through mathematical modeling and validation mechanisms.
Solution Approach 2:
The manual mechanical process of programming assembly code is replaced by an automated computational system based on Markov chains. The system substitutes human expertise with algorithmic generation, using statistical models to produce sequences that comply with execution constraints while significantly reducing the time required to generate large numbers of diverse sequences.
2Productivity
If random selection of instructions from the microprocessor's instruction dictionary is used, then generation speed increases, but the ability to obtain sequences with varied and precisely chosen characteristics is lost
Solution Approach 1:
The system changes parameters of the generation process by using a Markov chain model with configurable states representing different instruction types and memory access patterns. By adjusting the transition probabilities and initial state distribution, the system can precisely control the characteristics of generated sequences (such as memory access intensity, read/write ratios, and entropy) while maintaining high generation speed through automated computational processes.
Solution Approach 2:
The system incorporates feedback mechanisms by continuously monitoring the statistical properties of generated sequences (memory access patterns, instruction distribution) and adjusting the Markov chain transitions to achieve target characteristics. This feedback loop ensures that sequences have the desired variety and precision while maintaining efficient automated generation.
3Adaptability or versatility
If large sequences of several thousand instructions are generated rapidly with varied characteristics, then diversity of Memory Access Profiles is achieved, but difficulty in anticipating and quantifying memory contention behavior increases
Solution Approach 1:
The system performs preliminary action by generating diverse Memory Access Profiles with known and controlled characteristics before executing performance tests. By pre-generating sequences with specific memory access patterns (intensity, entropy, read/write ratios) and storing them in a database, the system enables subsequent WCET analysis and contention quantification to be performed on well-characterized inputs, making the measurement process more systematic and less uncertain.
Data Source
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AI summary
The invention relates to a method for automatically generating a sequence of Nmax instructions in assembly language, executable without error by a multi-core processor, comprising the steps of: - initializing the processor registers, then choosing a first instruction from the predetermined sequence, possibly at random; and - choosing an N+1st instruction, from among a read instruction in a memory connected to the processor cores by a memory bus, a write instruction in said memory, and a local instruction using only the processor registers, according to rules and priorities between said rules, said rules using respective differences in values of statistical metrics of a memory access profile (P) of the sequence of the N preceding instructions comprising values of statistical metrics, with reference values.