Assertion-Based Clock Verification for SoC Designs
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Solution Overview
Problem
Current clock verification methods for System-on-Chip (SoC) designs, particularly those using dynamic simulation-based checkers/monitors, are time-consuming, prone to human error, and not easily adaptable to last-minute changes, leading to delays and potential quality issues in verifying derived clocks.
Innovation Solution
The implementation of assertion-based verification methods, which involve counting clock cycles using state machines and verifying these counts with assertions written in an assertion-based language, allowing for efficient and adaptable verification of derived clocks without the need for extensive simulation cycles or test vectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dynamic simulation-based checkers/monitors are used for clock verification, then verification coverage can be achieved, but verification time becomes excessively long and the process is prone to human error
Solution Approach 1:
The patent replaces the mechanical simulation-based verification system with a mathematical assertion-based verification system. Instead of running time-consuming dynamic simulations with checkers/monitors, the invention uses formal assertions and mathematical proofs to verify clock relationships, thereby eliminating the time-consuming simulation cycles while maintaining verification accuracy.
Solution Approach 2:
The patent creates an abstract mathematical model that copies the essential verification requirements without needing the full physical simulation environment. By modeling clock relationships mathematically through assertions, the system verifies clock correctness without requiring extensive simulation test vectors and cycles.
2Reliability
If dynamic simulation-based verification is used, then clock verification can be performed, but adaptability to last-minute configuration changes is poor and requires re-testing with new test vectors
Solution Approach 1:
The patent makes the verification system dynamic and adaptable by using parameterized assertions that can be easily reconfigured. When clock configurations change, the verification model can be updated by modifying assertion parameters rather than rebuilding entire simulation test benches, enabling quick adaptation to last-minute changes without extensive re-testing.
Solution Approach 2:
The invention uses parameter-based assertions where verification criteria are defined by configurable parameters. When clock configurations change, only the relevant parameters need to be updated in the assertion model, allowing rapid adaptation to new requirements without the need to create new test vectors or rerun extensive simulations.
3Reliability
If simulation-based verification with multiple test vectors is used, then thorough verification can be achieved, but the building process is tedious and prone to human error
Solution Approach 1:
The patent extracts the essential verification logic from complex simulation setups and consolidates it into a unified assertion-based model. By separating the core verification requirements into mathematical assertions, the system eliminates the need for building complex checker/monitor circuits and extensive test vector sets, reducing setup complexity while maintaining verification thoroughness.
Solution Approach 2:
The invention creates a universal assertion-based verification framework that can verify multiple clock relationships using a single consistent methodology. This universal approach replaces the need for different verification setups for different clock pairs, reducing the tedious process of building and maintaining multiple simulation checkers while ensuring thorough verification across all clock relationships.
Data Source
AI summary
Methods and systems for verifying a derived clock using assertion-based verification. The method comprises counting the number of full or half cycles of a fast clock that occur between the rising edge and the falling edge of a slow clock (i.e. during the ON phase of the slow clock); counting the number of full or half cycles of the fast clock that occur between the falling edge and the rising edge of the slow clock (i.e. during the OFF phase of the slow clock); and verifying the counts using assertion-based verification.