Assertion Density Measurement in IC Verification
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Solution Overview
Problem
Existing methods for measuring assertion density in circuit design verification are syntax-based and do not effectively ensure that a circuit is well-covered, lacking a reliable way to ascertain sufficient coverage of circuit functionality.
Innovation Solution
A computerized method determines assertion density by computing predicates from a register-transfer language (RTL) description and simulation traces, using a figure of merit to optimize assertion generation, ensuring the set of assertions exceeds a predetermined threshold for efficient design verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If syntax-based methods (COI or MSD) are used to measure assertion density, then the measurement process is simple, but the measurement precision is insufficient to reflect actual functionality coverage
Solution Approach 1:
The patent changes the measurement parameter from syntax-based metrics (COI/MSD) to a functionality-based metric that counts the number of unique circuit functionalities covered by assertions. This transforms the measurement approach from structural analysis to behavioral analysis, improving precision by directly measuring what the assertions actually verify rather than just their syntactic properties
Solution Approach 2:
The patent introduces an intermediary process that extracts circuit functionalities from RTL descriptions and simulates assertion behavior to determine coverage. This intermediary layer translates between the assertion code and the actual circuit functionality, enabling precise measurement without requiring direct complex analysis of the assertion-syntax-circuit relationship
2Reliability
If the number of assertions is increased to improve coverage, then assertion density improves, but the complexity of managing and optimizing the assertion set increases
Solution Approach 1:
The patent implements a feedback mechanism where the assertion density measurement results are used to guide the generation and optimization of new assertions. The system continuously measures coverage, identifies uncovered functionalities, and generates targeted assertions to address gaps, creating a closed-loop process that improves reliability while managing complexity through data-driven decision making
Solution Approach 2:
The patent segments the circuit functionality into discrete, identifiable units that can be independently covered by assertions. By breaking down the overall verification task into coverage of individual functionalities rather than requiring comprehensive coverage of entire circuit blocks, the system achieves high reliability through targeted assertions while reducing the overall complexity of the assertion set
Data Source
AI summary
An assertion-based verification tool for circuit designs includes an effective measurement of assertion density for any given generated set of assertions. A register-transfer level (RTL) description of an integrated circuit (IC) is used to compute a set of predicates. Then, determination is made as to the number of predicates that are satisfiable on the given set of assertions received respective of the RTL description. Thereafter, simulation traces for the RTL are received and the number of predicates satisfiable on the simulation traces is computed. A figure of merit of assertion density is determined from the ratio of the respective numbers of predicates. The set of assertions may be modified as required to satisfy a predetermined threshold value of assertion density, to assure that a circuit is rigorously tested by the verification tool.