Hardware Assertion Reporting for Emulation Clocks
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Solution Overview
Problem
Current hardware-based verification systems for integrated circuits face challenges in efficiently reporting assertion information, particularly in emulation environments with dynamic targets where stopping the clock is not feasible, leading to performance degradation and loss of information.
Innovation Solution
A method and system for hardware-based reporting of assertion information using a user interface and assertion instrumentation code that generates hardware-based assertion instrumentation, allowing for efficient reporting and waveform capture without stopping the clock, utilizing a vectored OR-tree and sticky-bit circuits to optimize performance and reduce overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If hardware-based verification systems stop the clock to report assertion information, then assertion reporting accuracy is improved, but verification speed and productivity deteriorate
Solution Approach 1:
The patent pre-loads assertion information into buffer memory during normal operation before the clock stop is triggered. This preliminary action ensures that when the clock stops for assertion reporting, the data is already prepared and ready for immediate transfer to the host system, eliminating delays and maintaining high verification speed while ensuring accurate assertion reporting.
Solution Approach 2:
The patent implements buffer memory that continuously stores assertion information in advance, cushioning against the performance impact of clock stops. This buffer acts as a cushion that decouples the assertion reporting function from the main verification flow, allowing accurate reporting without repeatedly stopping the clock during normal operation.
2Measurement precision
If hardware-based verification systems continuously monitor all signals, then debugging accuracy is improved, but hardware resource consumption and device complexity increase
Solution Approach 1:
The patent segments the monitoring function by dividing the verification system into distinct modules: assertion evaluation logic, buffer memory for data storage, and host system for analysis. This segmentation allows the hardware to focus resources on specific assertion checks rather than continuously monitoring all signals, reducing device complexity while maintaining debugging accuracy through targeted monitoring.
Solution Approach 2:
The patent extracts the complex task of assertion information processing from the hardware verification system and transfers it to the host system. The hardware only needs to evaluate assertions and store results in buffer memory, while the host system performs the detailed analysis and debugging functions, significantly reducing hardware resource consumption while maintaining debugging accuracy.
3Loss of information
If assertion information is stored in buffer memory, then information retention is improved, but hardware resource consumption increases
Solution Approach 1:
The patent implements buffer memory that creates copies of assertion information for storage and later retrieval. This copying mechanism ensures that assertion data is retained and can be analyzed by the host system without requiring the hardware to continuously maintain all possible signal states, achieving information retention with moderate hardware resource consumption.
4Productivity
If the verification system integrates assertion evaluation logic in hardware, then verification speed is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements assertion evaluation logic that is integrated into the existing hardware verification system, allowing the same hardware infrastructure to serve multiple functions: normal verification operations and assertion evaluation. This multi-functionality approach increases verification speed without proportionally increasing device complexity, as the assertion logic leverages existing hardware resources.
Data Source
AI summary
A method and system for hardware based reporting of assertion information for emulation and hardware acceleration is disclosed. In one embodiment, a method of performing assertion-based verification, comprises providing a user interface to design assertions that aid in verifying an integrated circuit design. Assertion instrumentation code is generated to implement the assertions in hardware as assertion instrumentation. The assertion instrumentation code is provided to an emulator that generates the assertion instrumentation.