Assertion Extraction from Design Signal Traces
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Solution Overview
Problem
Traditional verification methods for complex semiconductor circuit designs, such as test benches, become inefficient in finding design errors and do not scale well for large electronic systems, requiring more effective techniques for error detection and verification.
Innovation Solution
A computer-implemented method for generating assertions by identifying signal groups, simulating circuits, dumping signal data, extracting relationships, and using a sliding temporal window to create truth tables, which are then filtered to produce syntactically correct assert, assume, and cover property statements for further simulation or formal verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional test bench methods are used for verification, then verification can be performed with simple procedures, but verification efficiency decreases and error detection capability becomes insufficient for complex circuits
Solution Approach 1:
The system enables self-service verification by automatically generating assertion properties from design descriptions without requiring manual intervention. The verification tool autonomously analyzes the circuit design, extracts signal relationships, and formulates verification assertions, eliminating the need for designers to manually create test cases and verification logic.
Solution Approach 2:
The patent replaces manual mechanical verification processes with automated computational analysis. Instead of designers manually creating and executing test benches, the system uses computer-based algorithms to automatically generate verification assertions, extract signal relationships from simulations, and perform formal verification, substituting human effort with automated intelligent systems.
2Reliability
If manual assertion writing is used, then assertions can be customized for specific designs, but the effort and time required increase significantly
Solution Approach 1:
The system enables self-service assertion generation by automatically analyzing design descriptions and generating appropriate assertion properties. The verification tool autonomously identifies critical signal relationships, extracts temporal dependencies from simulations, and formulates verification assertions without requiring designer intervention, thereby maintaining high reliability while eliminating time consumption.
Solution Approach 2:
The system performs preliminary analysis of the circuit design before verification execution. By pre-analyzing the design description, running simulations to extract signal relationships, and generating assertion templates in advance, the system prepares verification logic beforehand, reducing the time required during actual verification while ensuring comprehensive error detection coverage.
3Reliability
If comprehensive verification coverage is pursued for large circuits, then more design errors can be detected, but the verification process becomes too difficult and time-consuming to be viable
Solution Approach 1:
The system segments the verification process into distinct automated phases: design analysis, simulation execution, signal relationship extraction, assertion generation, and formal verification. By dividing the comprehensive verification task into manageable automated segments, the system achieves high verification coverage for large circuits while maintaining operational simplicity, as each segment is handled autonomously by the verification tool.
Solution Approach 2:
The patent replaces manual verification operations with automated computational systems. The verification tool automatically executes simulations, analyzes signal relationships, generates assertions, and performs formal verification without requiring manual intervention. This substitution enables comprehensive verification coverage for large-scale circuits while maintaining ease of operation, as the automated system handles the complexity internally.
Data Source
AI summary
Groups of signals in an electronic design for which interesting assertions, such as assert, assume and cover properties, can be generated are identified. A sliding temporal window of fixed depth is used to sample unique present and past value combinations of signals in the signals groups generated by one or more simulations or emulations. The values of signals in the signal groups are organized into truth tables. Minimal functional relations are extracted from the truth tables, using techniques similar to those for synthesis of partial finite memory machines from traces, and used to generate assertions. The assertions are filtered using a cost function and pertinence heuristics, and a formal verification tool used to prune unreachable properties and generate traces for reachable cover properties. Syntactically correct assert, assume and cover property statements for the generated properties are instantiated and packaged into a file suitable for further simulation or emulation or formal verification.