Assertion Statement Debugging via State Representation Analysis
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Solution Overview
Problem
Designers face challenges in debugging assertion statements during functional verification of circuit designs, as failures may not identify bugs in the circuit but rather in the assertion statements themselves, leading to inefficient debugging processes.
Innovation Solution
A computing system is used to check and generate corrected assertion statements by extracting sequence items, creating a state representation, and modifying patterns to identify and fix errors in assertion statements, ensuring they conform to design specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If designers manually debug assertion statements by introducing mutations or utilizing recorded waveform data, then assertion statement errors can be located and fixed, but the debugging process becomes time-consuming and inefficient
Solution Approach 1:
The system performs preliminary analysis of assertion statements by extracting sequence items and generating state representations before full simulation. This preliminary action identifies potential errors early, allowing designers to fix assertion statement defects before they cause time-consuming simulation failures, thus reducing overall debugging time while maintaining detection accuracy
Solution Approach 2:
The system introduces an intermediary analysis layer between the assertion statements and simulation execution. This intermediary extracts sequence items, generates state representations, and compares actual states with expected states, serving as a mediator that identifies errors without requiring full simulation runtime, thereby reducing debugging time while preserving error detection capability
2Productivity
If design verification tools stop checking conditions in assertion statements during simulation in response to a violation, then simulation efficiency is improved, but errors in assertion statements themselves may not be identified
Solution Approach 1:
The system segments the verification process into two parts: (1) extraction of sequence items and generation of state representations from assertion statements, and (2) comparison of actual states with expected states. This segmentation allows the system to verify assertion statement correctness independently of simulation execution, maintaining both simulation efficiency and assertion statement reliability
Solution Approach 2:
The system performs preliminary extraction of sequence items and generation of state representations before simulation execution. This preliminary action enables the system to identify errors in assertion statements without requiring simulation to continue, thus maintaining simulation efficiency while improving assertion statement correctness verification
Data Source
AI summary
This application discloses a computing system to check and generate an assertion statement. The assertion statement, when executed during a simulation of a circuit design, can verify a simulated behavior of the circuit design. The computing system can extract sequence items from the assertion statement, and generate a state representation for the sequence items based on the simulated behavior of the circuit design. The state representation can identify states of the extracted sequence items at different clock ticks of the simulation. The computing system can locate an error in the assertion statement based on the state representation by generating patterns from sequence operators in the assertion statement and comparing the patterns to the state representation. The computing system can utilize the error in the assertion statement to generate a corrected assertion statement. The computing system can utilize propagate-and-repeat functionality to generate assertions by determining when to check each sequence item.