Hierarchical Assertion Verification Graph for IC Simulation
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Solution Overview
Problem
Current electronic design automation (EDA) systems face challenges in efficiently verifying complex assertions during integrated circuit design simulation, leading to high computational burdens and delayed reporting of assertion satisfaction or violation.
Innovation Solution
The integration of assertions into a simulation environment using a hierarchical graph of processing elements, where operator nodes and leaf nodes are arranged in a tree structure, allowing for efficient parallel execution and prompt reporting of assertion verification results through MATCH and DONE signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If assertions are integrated into simulation environment using hierarchical graph of processing elements, then assertion verification speed and efficiency are improved, but computational complexity and system structure complexity increase
Solution Approach 1:
The assertion verification system is segmented into a hierarchical graph of processing elements, where each processing element handles specific assertion evaluation tasks. This segmentation allows parallel execution of multiple assertions simultaneously, improving verification speed while distributing computational complexity across modular units rather than concentrating it in a single monolithic structure.
Solution Approach 2:
The patent introduces a hierarchical dimension to the assertion verification system by organizing processing elements in multiple levels. This hierarchical arrangement enables concurrent evaluation of assertions at different levels of the design hierarchy, effectively adding a temporal and structural dimension that accelerates verification without linearly increasing overall system complexity.
2Productivity
If multiple complex assertions are verified concurrently, then verification coverage and efficiency are improved, but computational resource consumption increases
Solution Approach 1:
Complex assertions are segmented into smaller sub-assertions and evaluation tasks that can be distributed across multiple processing elements. This segmentation enables concurrent verification of multiple assertions using computational resources in parallel, thereby improving verification coverage while optimizing resource utilization through efficient load distribution rather than sequential processing that would consume resources over a longer period.
3Productivity
If hierarchical arrangement of operator nodes and leaf nodes is used, then assertion evaluation efficiency is improved, but system complexity and implementation difficulty increase
Solution Approach 1:
The assertion evaluation system is segmented into operator nodes that perform logical operations and leaf nodes that represent input signals or sub-expressions. This segmentation creates a hierarchical structure where complex assertions are broken down into manageable operational units, improving evaluation efficiency while making the system more implementable through modular design patterns.
Solution Approach 2:
Operator nodes serve as intermediaries between leaf nodes (input signals) and the final assertion evaluation result. These intermediary nodes process and combine inputs according to logical operators, enabling efficient hierarchical evaluation while abstracting the complexity of direct signal-to-result connections, thereby improving efficiency without proportionally increasing implementation difficulty.
4Loss of time
If prompt reporting of assertion satisfaction or violation is implemented, then verification feedback time is reduced, but system complexity and processing overhead increase
Solution Approach 1:
The hierarchical processing structure performs preliminary evaluation of assertion components as they become available, rather than waiting for complete simulation cycles. Operator nodes prepare and partially evaluate assertions in advance, enabling prompt reporting of assertion satisfaction or violation as soon as sufficient information is available, thereby reducing feedback time without requiring complete re-evaluation of all assertions.
Data Source
AI summary
A method for design verification includes receiving a definition of a design of an integrated circuit device and at least one assertion of a property that is to be verified over the design. The definition is compiled into a graph of processing elements, including first processing elements that simulate operation of the device and at least one second processing element representing the at least one assertion. The at least one second processing element includes a hierarchical arrangement of at least one operator node and one or more leaf nodes corresponding to inputs of the at least one assertion. A simulation of the design is executed by triggering the processing elements in the graph in multiple, consecutive clock cycles and evaluating the property during execution of the simulation.