Assertion Development Tool Waveform Testing IC Verification
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Solution Overview
Problem
Current integrated circuit design verification techniques, particularly simulation methods using Hardware Description Languages (HDL) and assertions, are inefficient and resource-intensive, especially when dealing with complex designs like ASICs, FPGAs, and SoC devices, as they require extensive processing resources and time-consuming simulations.
Innovation Solution
An assertion development tool that allows for the preparation, testing, and modification of assertions using integrated circuit waveforms, enabling efficient evaluation and visualization of assertion operations, reducing the need for full simulations by utilizing a waveform database and user interface for iterative refinement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full integrated circuit simulations are performed to test assertions, then verification accuracy is improved, but simulation time and processing resources increase significantly
Solution Approach 1:
The patent applies preliminary action by pre-generating and storing waveform data before assertion testing. The system creates a database of waveforms that can be quickly retrieved and applied to assertions without requiring full simulations, thereby reducing verification time while maintaining accuracy through pre-computed test cases.
Solution Approach 2:
The patent uses copying by creating simplified waveform representations and assertions that replicate the essential behavior of complex circuit scenarios. Instead of simulating entire circuits, the system copies key waveform patterns into a database and reuses them for assertion evaluation, significantly reducing computational resources required for verification.
2Reliability
If comprehensive simulation testing is performed for assertions, then verification thoroughness is improved, but processing resources and cost increase
Solution Approach 1:
The patent extracts the essential waveform characteristics from complex circuit simulations and separates them into a reusable database. By taking out only the critical waveform patterns needed for assertion validation, the system eliminates unnecessary computational overhead while maintaining thorough verification through targeted extraction of essential test cases.
Solution Approach 2:
The patent applies parameter changes by transforming full circuit simulations into simplified waveform parameter sets. Instead of running complete simulations for each assertion, the system changes the input parameters to pre-generated waveform patterns, reducing processing resources while maintaining verification thoroughness through parameterized test cases.
3Reliability
If iterative assertion modification and retesting is performed, then assertion accuracy is improved, but time consumption increases
Solution Approach 1:
The patent implements feedback by automatically evaluating assertions against the waveform database and providing immediate results on assertion correctness. The system feeds back whether an assertion passes or fails against stored waveforms, enabling rapid iterative modification without requiring time-consuming full simulations for each modification cycle.
Solution Approach 2:
The patent applies preliminary action by pre-preparing the waveform database before assertion development begins. This allows developers to iteratively modify assertions and immediately test them against ready-to-use waveforms, eliminating the time lag associated with regenerating test cases for each modification and significantly improving development efficiency.
Data Source
AI summary
One embodiment of the present application includes the preparation of an assertion for inclusion in an integrated circuit simulation performed with a processing device (21). In response to an input to this processing device (21), a set of integrated circuit waveforms are defined to test the assertion. The processing device (21) tests the assertion with these waveforms; and after successful testing, the integrated circuit simulation is performed with the assertion.