Assist Gate Structures for 3D Vertical Memory Current Flow
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Solution Overview
Problem
Three-dimensional (3D) memory devices face high resistance issues due to uneven current paths caused by the stairstep structure of semiconductor pads, leading to complex control circuitry and reduced operational efficiency.
Innovation Solution
The introduction of an assist gate structure that creates a local inversion channel between the semiconductor pads and the semiconductor strips, reducing resistivity and improving current flow paths by applying a gate voltage to the assist gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If stairstep structure of semiconductor pads is used to provide landing areas for interlayer conductors, then connection between layers is enabled, but resistance in current paths becomes high and uneven
Solution Approach 1:
An assist gate structure is introduced as an intermediary element between the semiconductor pads and the semiconductor strips. This assist gate creates a local inversion channel that acts as a mediator to improve current flow, reducing the resistance problem caused by the stairstep pad structure while maintaining the manufacturing benefits of the stairstep design.
Solution Approach 2:
The assist gate structure applies local quality by creating a localized inversion channel only in specific regions where current flow needs improvement. Rather than changing the entire pad structure, the inversion channel is formed locally at the interface between the assist gate and the semiconductor strips,针对性地 reducing resistance in critical current paths.
2Ease of manufacture
If stairstep structure of semiconductor pads is used, then interlayer connections are provided, but control circuitry becomes complex
Solution Approach 1:
The assist gate structure serves as a mediator that simplifies control circuitry by providing a uniform interface for current flow. Instead of complex control mechanisms needed to manage uneven current paths through the stairstep structure, the assist gate creates consistent inversion channels that facilitate simpler, more uniform control of current flow across all interlayer connections.
3Device complexity
If conventional gate structures are used without assist gates, then device structure is simpler, but current flow paths are uneven and resistivity is high
Solution Approach 1:
The assist gate structure is positioned as an intermediary between the conventional gate and the semiconductor strips. It creates a local inversion channel that mediates the current flow, ensuring uniform distribution without requiring complete redesign of the overall device structure. This maintains relative structural simplicity while dramatically improving current flow uniformity.
Solution Approach 2:
Rather than fundamentally changing the entire device structure, the assist gate applies local quality by creating inversion channels only where needed - at the critical interface regions between gates and semiconductor strips. This localized approach improves current flow uniformity without adding excessive structural complexity throughout the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces the resistivity in current paths from the semiconductor pads to the memory cells, enhancing the operational efficiency and stability of 3D memory devices by creating a more uniform and efficient current flow.
Implementation Method 1
Bias circuitry can be connected to the assist gate structure to apply a gate voltage in response to addresses selecting a memory cell in a block when the select gate structure is turned on. Applying a gate voltage to the assist gate structure can cause a local inversion channel (i.e., an increase in the concentration of charge carriers) to form in the semiconductor strips near the assist gate structure, and reduce resistivity in current paths from the semiconductor pads to the memory cells on the semiconductor strips.
Data Source
AI summary
A 3D array of memory cells with one or more blocks is described. The blocks include a plurality of layers. The layers in the plurality include semiconductor strips which extend from a semiconductor pad. The layers are disposed so that the semiconductor strips in the plurality of layers form a plurality of stacks of semiconductor strips and a stack of semiconductor pads. Also, a plurality of select gate structures are disposed over stacks of semiconductor strips in the plurality of stacks between the semiconductor pad and memory cells on the semiconductor strips. In addition, different ones of the plurality of select gate structures couple the semiconductor strips in different ones of the stacks of semiconductor strips to the semiconductor pads in the plurality of layers. Further, an assist gate structure is disposed over the plurality of stacks between the select gate structures and the stack of semiconductor pads.