Multi-Level Non-Volatile Memory Assist Gate Programming
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Solution Overview
Problem
Conventional non-volatile memory devices require multiple programming steps and long times to achieve accurate threshold voltage distribution for multi-level memory cells, leading to inefficiencies in programming and erasing operations.
Innovation Solution
The introduction of a multi-level non-volatile memory structure with a control gate, charge storage layer, doped region, select gate, and assist gate, along with specific dielectric layers and spacers, allows for source side injection programming and enhanced erasing through channel self-boosting and concentrated electric fields, reducing programming time and increasing erasing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional NOR non-volatile memory is used for multi-level memory cells, then data storage capability is improved, but programming time increases and reliability deteriorates due to multiple programming steps and small threshold voltage distribution range
Solution Approach 1:
The invention divides the memory cell structure into distinct functional components: control gate, charge storage layer, select gate, and assist gate. This segmentation allows independent optimization of each component's function, enabling faster programming through the assist gate's channel formation capability while maintaining multi-level storage capability through the charge storage layer.
Solution Approach 2:
The assist gate acts as an intermediary element that forms a channel to accelerate electron injection into the charge storage layer during programming. This intermediary structure enables source-side injection programming, significantly reducing programming time compared to conventional methods that rely solely on control gate voltage.
2Quantity of substance
If conventional NOR non-volatile memory is used for multi-level memory cells, then data storage capability is improved, but the number of programming steps increases and device reliability deteriorates
Solution Approach 1:
By segmenting the memory cell into control gate, charge storage layer, select gate, and assist gate, the invention enables more precise control over the programming process. The assist gate specifically handles channel formation for electron injection, while the select gate controls electron extraction during erasing, allowing threshold voltages to be more accurately positioned within desired ranges and reducing programming step complexity.
Solution Approach 2:
The invention changes the electrical parameters by introducing the assist gate that can independently control channel formation and the select gate that can independently control electron extraction. This parameter control enables more precise threshold voltage positioning, reducing the need for multiple programming confirmation steps and improving device reliability.
3Ease of operation
If conventional NOR array structure is used, then reading and writing operations can be performed randomly, but each memory cell occupies larger area due to sharing contact window and source line
Solution Approach 1:
The invention adds vertical dimension to the memory cell structure by stacking the control gate, charge storage layer, and select gate in layers. This three-dimensional arrangement increases storage density without compromising the planar footprint, allowing random access capability to be maintained while reducing the area occupied by each memory cell.
4Quantity of substance
If conventional NOR non-volatile memory is used for multi-level memory cells, then data storage capability is improved, but manufacturing complexity increases and process window decreases
Solution Approach 1:
The segmented structure with distinct control gate, charge storage layer, select gate, and assist gate allows each component to be optimized and fabricated using specialized processes. This segmentation simplifies the overall manufacturing by enabling independent process optimization for each layer, reducing the complexity of integrating multiple functions into a single structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration simplifies manufacturing, reduces costs, and improves the integration and reliability of the device by enabling faster programming and more efficient erasing operations, with accurate control of threshold voltages within predetermined ranges.
Implementation Method 1
An inversion layer is formed in the substrate below the assist gate when a voltage is applied to the assist gate
Implementation Method 2
The charge storage layer is disposed between the control gate and the substrate
Data Source
AI summary
A multi-level non-volatile memory including a memory cell disposed on a substrate is provided. The memory cell includes a control gate, a charge storage layer, a doped region, a select gate, and an assist gate. The control gate is disposed on the substrate. The charge storage layer is disposed between the control gate and the substrate. The doped region is disposed in the substrate at the first side of the control gate. The select gate is disposed on the sidewall of the first side of the control gate and on the substrate between the control gate and the doped region. The assist gate is disposed on the sidewall of the second side of the control gate. An inversion layer is formed in the substrate below the assist gate when a voltage is applied to the assist gate.