Assistant Patterns for Semiconductor Critical Dimension Measurement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current wafer metrology tools struggle to accurately measure both large and small features on semiconductor integrated circuits due to limitations in their critical dimension measurement capabilities, leading to significant measurement errors and challenges in maintaining spatial relationships during IC manufacturing.
Innovation Solution
The introduction of assistant patterns in the IC design layout, specifically adjacent to large main patterns, allows for accurate measurement of critical dimensions by utilizing smaller assistant patterns that can be measured with high precision by existing tools, thereby enabling accurate determination of the main pattern dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If wafer metrology tools are used to measure large critical dimensions (e.g., 10 μm), then the measurement range is sufficient, but the measurement accuracy deteriorates significantly (error of 100 nm or more)
Solution Approach 1:
The patent introduces assistant patterns as intermediary reference structures that are measured with high accuracy by wafer metrology tools. These assistant patterns serve as mediators to indirectly determine the dimensions of large main patterns, avoiding direct measurement of the large features which would suffer from poor accuracy. The assistant patterns act as a bridge between the measurement tool's capabilities and the required measurement precision for large features.
Solution Approach 2:
The patent replaces the direct mechanical/optical measurement system with an indirect calculation-based approach. Instead of using the wafer metrology tool to directly measure large patterns (mechanical/optical system), the method substitutes this with measuring smaller assistant patterns and calculating the main pattern dimensions through mathematical relationships, thereby achieving high precision without direct measurement.
2Measurement precision
If assistant patterns are added to the IC layout, then measurement accuracy for large features is improved, but the device complexity increases
Solution Approach 1:
The patent segments the measurement task into two parts: measuring small assistant patterns with high accuracy and calculating the dimensions of large main patterns through mathematical relationships. This segmentation allows the measurement system to focus on measuring only the small, easily measurable assistant patterns while deriving information about large patterns through calculation, thereby maintaining high accuracy without requiring complex direct measurement capabilities.
Data Source
AI summary
A method includes receiving an integrated circuit (IC) layout having a pattern layer. The pattern layer includes a main layout pattern. A dimension W1 of the main layout pattern along a first direction is greater than a wafer metrology tool's critical dimension (CD) measurement upper limit. The method further includes adding a plurality of assistant layout patterns into the pattern layer. The plurality of assistant layout patterns includes a pair of CD assistant layout patterns on both sides of the main layout pattern along the first direction. The pair of CD assistant layout patterns have a substantially same dimension W2 along the first direction and are about equally distanced from the main layout pattern by a dimension D1. The dimensions W2 and D1 are greater than a printing resolution in a photolithography process and are equal to or less than the wafer metrology tool's CD measurement upper limit.