Associative Cache Bank Select Table Parallel Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multiple-bank associative caches perform better than direct-mapped caches but suffer from longer access times due to the added burden of address comparisons, necessitating methods to combine the fast access of direct-mapped caches with the performance advantages of associative caches.
Innovation Solution
Implementing a method and circuitry that access an associative cache by reading a bank select table in parallel with data access, determining whether the access is a cache hit, miss, or mispredict, and using a least recently used replacement table to optimize bank selection and replacement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multiple-bank associative cache is used, then cache hit ratio is improved, but access time increases due to address comparison burden
Solution Approach 1:
The patent pre-calculates and stores bank selection information in a bank select table before actual cache access occurs. When an address is accessed, the corresponding bank selection is already determined and stored, eliminating the need for real-time address comparison across multiple banks. This preliminary preparation resolves the contradiction by maintaining high cache hit ratios while reducing access time to direct-mapped cache speeds.
Solution Approach 2:
The patent introduces a bank select table as an intermediary structure between the cache address and the actual data storage locations. This intermediary pre-maps addresses to specific banks, acting as a mediator that directs access without requiring complex real-time comparisons. The bank select table enables the system to achieve associative cache performance with direct-mapped access speed, resolving the time-hit ratio contradiction.
2Productivity
If address comparison is performed in multiple banks, then cache performance is improved, but access speed decreases
Solution Approach 1:
The bank select table pre-determines which bank should contain data for each address before access occurs. This preliminary action stores the optimal bank selection in advance, allowing the cache to achieve high performance by directly accessing the predetermined bank without performing slow address comparisons during actual access operations.
Solution Approach 2:
The patent segments the cache access function into two parts: a bank selection function (handled by the bank select table) and a data access function. By separating these functions, the system can maintain high access speed while still achieving the performance benefits of multi-bank associative caching, as the bank selection is already determined and stored separately.
3Loss of time
If a direct-mapped cache is used, then access time is reduced, but cache hit ratio decreases
Solution Approach 1:
The bank select table serves multiple functions: it acts as a direct-mapped index for fast access, while simultaneously providing the bank selection information needed for associative cache operation. This multi-functional structure allows the system to achieve both fast access times and high cache hit ratios by combining the simplicity of direct-mapped indexing with the flexibility of associative caching.
Solution Approach 2:
The bank select table acts as an intermediary that enables direct-mapped access speed while providing associative cache functionality. By pre-storing bank selection information, it mediates between the simple access path of direct-mapped caches and the intelligent bank selection of associative caches, achieving both fast access and high hit ratios simultaneously.
Data Source
AI summary
A circuit for accessing an associative cache is provided. The circuit includes data selection circuitry and an outcome parallel processing circuit both in communication with the associative cache. The outcome parallel processing circuit is configured to determine whether an accessing of data from the associative cache is one of a cache hit, a cache miss, or a cache mispredict. The circuit further includes a memory in communication with the data selection circuitry and the outcome parallel processing circuit. The memory is configured to store a bank select table, whereby the bank select table is configured to include entries that define a selection of one of a plurality of banks of the associative cache from which to output data. Methods for accessing the associative cache are also described.