Associative Memory Block Addressing for Parallel Data Access
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Solution Overview
Problem
Conventional memory systems face inefficiencies in handling bad blocks, leading to reduced performance and increased production costs due to the need for controller intervention and inefficient utilization of memory arrays when bad blocks are marked as unusable, even if they are still viable.
Innovation Solution
The solution involves associative mapping of blocks across multiple memory arrays to allow for alternating or parallel data access, utilizing address translators to logically address good blocks contiguously and map bad blocks to higher addresses, thereby optimizing memory usage and reducing access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bad blocks are marked as unusable to ensure data reliability, then memory reliability is improved, but memory capacity and productivity deteriorate
Solution Approach 1:
The patent converts the harmful effect of bad blocks into a beneficial outcome by using associative mapping to redirect accesses to good blocks. Instead of discarding bad blocks entirely, the system maps logical addresses to available good blocks in a way that maintains data reliability while preserving memory capacity. This transforms the presence of bad blocks from a purely negative factor into an opportunity for optimized memory organization and field repairs.
Solution Approach 2:
The patent changes the addressing parameter from direct physical addressing to associative logical addressing. By introducing an address translation layer that maps logical addresses to physical block locations, the system can dynamically select good blocks for data storage while avoiding bad blocks. This parameter change enables the memory system to maintain high reliability through careful address mapping while preserving productive use of available memory capacity.
2Reliability
If controller intervention is used to handle bad blocks, then memory reliability is improved, but access time and device complexity worsen
Solution Approach 1:
The patent implements preliminary action by pre-establishing an associative mapping table that contains alternative good block locations for each logical address before data access occurs. When a bad block is detected, the mapping table already contains the alternative location, eliminating the need for real-time controller intervention and search. This preliminary preparation of replacement block information significantly reduces access time while maintaining reliability.
Solution Approach 2:
The patent introduces an address translation intermediary layer that sits between the controller and physical memory blocks. This intermediary maintains the associative mapping table and performs address translation automatically, reducing the burden on the main controller. The intermediary handles bad block redirection transparently and rapidly, improving access time while ensuring data reliability through systematic address mapping.
3Device complexity
If sequential access to multiple memory arrays is used, then device complexity is reduced, but data throughput and productivity worsen
Solution Approach 1:
The patent applies segmentation by dividing the memory access process into independent parallel operations. Instead of sequentially accessing multiple memory arrays one after another, the system organizes memory blocks into segments that can be accessed simultaneously through the associative mapping structure. Each memory array can be accessed in parallel based on the mapped logical addresses, significantly increasing data throughput while maintaining manageable device complexity through systematic organization.
Solution Approach 2:
The patent transitions from one-dimensional sequential access to multi-dimensional parallel access by introducing the associative mapping dimension. The mapping table adds a new dimension to the address space, allowing the system to access multiple memory arrays simultaneously by translating a single logical address into multiple physical block locations across different arrays. This dimensional change enables parallel data retrieval while keeping the control logic relatively simple.
4Reliability
If bad blocks are replaced with spare blocks during production, then memory reliability is improved, but manufacturing cost and device complexity worsen
Solution Approach 1:
The patent applies universality by making good blocks serve multiple functions: they can store user data and simultaneously serve as replacement blocks for bad blocks through the associative mapping mechanism. Instead of dedicating separate spare blocks solely for replacement purposes, the system allows any good block to fulfill the replacement role as needed. This multi-functionality reduces the number of dedicated spare blocks required, lowering manufacturing costs while maintaining high reliability through flexible block substitution.
Data Source
AI summary
Apparatus and methods provide associative mapping of the blocks of two or more memory arrays such that data, such as pages of data, from the good blocks of the two or more memory arrays can be read in an alternating manner for speed or can be read in parallel for providing data to relatively wide data channels. This obviates the need for processor intervention to access data and can increase the throughput of data by providing, where configured, the ability to alternate reading of data from two or more arrays. For example, while one array is loading data to a cache, the memory device can be providing data that has already been loaded to the cache.