Associative Processing Memory for Parallel Redundant Computing
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Solution Overview
Problem
Existing memory systems face challenges in efficiently performing computational operations due to bandwidth constraints and increased latency, particularly in serial processing methods that rely on bit-serial operations and vector length, leading to prolonged arithmetic operation times.
Innovation Solution
Implementing an associative processing memory (APM) system that performs redundant computational operations in parallel across multiple planes, using different assumptions for arithmetic output bits and correcting results based on actual values, thereby reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If serial processing methods are used for computational operations, then device complexity is reduced, but processing time increases and productivity decreases
Solution Approach 1:
The patent divides the computational task into multiple segments by processing different bit positions in parallel across multiple cycles. Each cycle handles a specific bit position (e.g., least significant bit, most significant bit) simultaneously for multiple operations, transforming serial bit processing into parallel cycle-based processing.
Solution Approach 2:
The patent introduces a time dimension by using multiple processing cycles, where each cycle operates in parallel on different bit positions. This transforms the single-dimensional serial processing into multi-dimensional parallel processing across time cycles, effectively increasing throughput without proportionally increasing hardware complexity.
2Quantity of substance
If vector length is increased for computational operations, then processing capacity is improved, but latency increases due to serial processing
Solution Approach 1:
The patent segments the vector processing into bit-position-based segments, where each processing cycle handles a specific bit position across all vector elements. This allows longer vectors to be processed by dividing work across multiple cycles, each operating in parallel on their assigned bit position, thereby maintaining low latency per cycle while supporting extended vector lengths.
Solution Approach 2:
The patent performs preliminary organization of data by bit positions before processing, arranging vector elements so that corresponding bits are aligned for parallel processing. This preliminary arrangement enables each processing cycle to immediately operate on the correct bit positions without additional sequencing delays, reducing overall latency for long vector operations.
3Speed
If bandwidth constraints are addressed by increasing interface capacity, then data transfer speed is improved, but interface complexity and cost increase
Solution Approach 1:
The patent ensures continuous useful action by keeping the processing unit actively computing across multiple cycles without idle等待 periods. Each cycle processes a different bit position, maintaining constant computational throughput. This continuous processing effectively increases the usable bandwidth of the interface by maximizing the utilization of existing transfer capacity.
Solution Approach 2:
The patent implements periodic action through cyclic processing modes, where each cycle processes a specific bit position in a repeating sequence. This periodic structure allows the interface to operate at its maximum sustained rate by continuously feeding data in regular intervals, effectively increasing throughput without requiring peak bandwidth that would demand more complex interface hardware.
Data Source
AI summary
Methods, systems, and devices for redundant computing across planes are described. A device may perform a computational operation on first data that is stored in a first plane that includes content-addressable memory cells. The first data may be representative of a set of contiguous bits of a vector. The device may perform, concurrent with performing the computational operation on the first data, the computational operation on second data that is stored in a second plane. The second data may be representative of the set of contiguous bits of the vector. The device may read from the first plane and write to the second plane, third data representative of a result of the computational operation on the first data.