Associative Square Root Calculation Without Data Shifting
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Solution Overview
Problem
Existing digital methods for calculating square roots of binary numbers are computationally intensive due to the requirement of explicit data-shifting operations and subtraction on potentially large numbers of bits, contributing to high computational load and latency.
Innovation Solution
A method and calculator utilizing an associative processing unit (APU) with a memory array organized into columns and rows, where operations are performed concurrently by activating specific rows and registers to form operands and guesses, eliminating the need for data-shifting and handling only the currently active bits in each iteration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If explicit data-shifting operations are performed in each iteration of the square root calculation, then the calculation follows the traditional iterative method, but the computational load and latency increase
Solution Approach 1:
The patent extracts and eliminates the data-shifting operation from the iterative square root calculation process. By using an associative processing unit that can directly access and operate on memory rows, the method removes the shifting step that traditionally precedes each subtraction operation, thereby reducing computational complexity while maintaining calculation accuracy
Solution Approach 2:
The patent replaces the mechanical data-shifting operation with a memory access operation. Instead of physically shifting bits through multiple clock cycles, the associative processing unit directly activates specific rows in memory containing the radicand and previously calculated bits, substituting a complex mechanical operation with a simpler memory access and comparison operation
2Reliability
If data-shifting operations are performed on large numbers of bits in each iteration, then the traditional iterative method is followed, but the latency of the overall process increases
Solution Approach 1:
The patent removes the time-consuming data-shifting operation from each iteration. By eliminating this operation entirely and using direct memory row activation, the method significantly reduces the time required for each iteration while preserving the correctness of the bit-by-bit square root calculation
Solution Approach 2:
The patent prepares the data in advance by storing the radicand and intermediate results in specific memory row configurations. This preliminary organization allows subsequent iterations to directly access the required data without performing shifting operations, thereby reducing latency while maintaining calculation correctness
3Reliability
If traditional iterative square root calculation methods are used, then sequential processing is performed, but the productivity for calculating multiple square roots decreases
Solution Approach 1:
The patent merges multiple square root calculations into a single parallel execution framework. By storing multiple radicands in different columns of the memory array and using column-selective operations, the associative processing unit can calculate multiple square roots simultaneously, dramatically increasing productivity while maintaining the accuracy of each individual calculation
Solution Approach 2:
The patent transitions from sequential one-dimensional processing to parallel two-dimensional processing by utilizing the memory array's row-column structure. Multiple calculations are performed in parallel across different columns while sharing common row operations, effectively adding a spatial dimension to the calculation process and thereby increasing throughput
Data Source
AI summary
A calculator for calculating a plurality of square roots includes a memory array, at least two registers, a bit subtractor, and a controller. The memory array is organized into columns and rows. The registers store a fixed value. The controller, operatively coupled to the other components, allocates a first set of rows to test variables and a second set to result variables, and initially stores each of a plurality of radicands in a separate column. For multiple iterations, the controller concurrently activates selections of rows to form current operands and current guesses for each column. The controller then instructs the bit subtractor to perform subtraction operations. For each column with a positive subtraction result, the controller selectively writes a new bit of the square root and selectively overwrites values with a new remainder derived from the subtraction result, without performing an explicit data-shifting operation.