Associative Structure for Transactional Memory False Positive Reduction
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Solution Overview
Problem
Transactional memory systems face limitations in tracking large read sets due to hardware resource constraints, leading to pessimistic cache conflicts and false positives, particularly in cache-based systems where eviction can cause system-wide issues.
Innovation Solution
A system and method that utilize a second associative structure with different granularity to filter out false positives by monitoring accessed and dirty bits in page tables, allowing protection of larger memory areas and employing an overlapping range cache to track speculatively accessed locations, with the option to use a translation lookaside buffer (TLB) for efficient query and protection mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If cache-based transactional memory systems track large read sets, then more memory areas can be protected, but cache conflicts cause false positives and system reliability deteriorates
Solution Approach 1:
The patent divides the cache index into multiple sub-indices and tracks speculative data at a coarser granularity level. Instead of tracking every individual cache line, the system tracks at the sub-index level, which reduces the number of tracking entries and minimizes false positives while still providing comprehensive memory area protection.
Solution Approach 2:
The patent introduces a sub-index structure as an intermediary between the cache index and the speculative data tracking. This sub-index acts as a mediator that aggregates multiple cache lines into larger groups, allowing the system to track memory areas more efficiently without the overhead of tracking every individual cache line, thus reducing false positives.
2Productivity
If hardware-based transactional memory uses speculative data buffers, then memory operations can be executed speculatively, but hardware resource limitations restrict the size of transactions
Solution Approach 1:
The patent changes the granularity parameter of the tracking structure from fine-grained (individual cache lines) to coarse-grained (sub-indices). This parameter change allows the system to track larger memory areas with fewer hardware resources, as the sub-index structure requires significantly less space than tracking every individual cache line separately.
Solution Approach 2:
The patent introduces a hierarchical dimension to the tracking structure by adding sub-indices between the cache index and the speculative data. This dimensional addition allows the system to organize tracking data in a multi-level hierarchy, which improves scalability and reduces the hardware resources needed for tracking large read sets.
3Device complexity
If cache lines are evicted during transaction execution, then hardware resources are freed, but tracked data may be lost causing incorrect transaction outcomes
Solution Approach 1:
The patent performs preliminary tracking of speculative data at the sub-index level before cache evictions occur. By establishing the tracking structure in advance and organizing data at a coarser granularity, the system ensures that even if individual cache lines are evicted, the aggregated sub-index data remains intact and can be used to correctly determine transaction outcomes.
Data Source
AI summary
A system and method are disclosed for allowing protection of larger areas than memory lines by monitoring accessed and dirty bits in page tables. More specifically, in some embodiments, a second associative structure with a different granularity is provided to filter out a large percentage of false positives. By providing the associative structure with sufficient size, the structure exactly specifies a region in which conflicting cache lines lie. If entries within this region are evicted from the structure, enabling the tracking for the entire index filters out a substantial number of false positives (depending on a granularity and a number of indices present). In some embodiments, this associative structure is similar to a translation look aside buffer (TLB) with 4 k, 2M entries.