ASTC Interpolation Using Binary Logic for Smaller Decoding Hardware
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Solution Overview
Problem
Decoding hardware for Adaptive Scalable Texture Compression (ASTC) can be costly in terms of hardware resources and silicon area due to the complexity of interpolating between endpoint values.
Innovation Solution
A binary logic circuit is used to perform interpolation calculations between ASTC colour endpoint values using a weighting index, reducing the size and processing time by interpolating between lower-bit colour endpoint components and applying logical processing operations to generate the final result.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional interpolation methods using 16-bit endpoint components are used, then interpolation precision is maintained, but hardware resource consumption and silicon area increase
Solution Approach 1:
The interpolation process is segmented into two stages: first performing interpolation with lower-bit (8-bit or 12-bit) colour endpoint components to generate intermediate results, then applying logical processing operations to produce the final 16-bit interpolated result. This segmentation allows the hardware to use simpler, smaller components while maintaining overall precision through the two-stage process.
Solution Approach 2:
The patent extracts and processes only the necessary bit portions of the colour endpoint components. By performing interpolation on lower-bit components and then applying selective logical operations, the system extracts only the essential information needed for accurate interpolation, avoiding the need to process all 16 bits throughout the entire process, thus reducing hardware complexity.
2Measurement precision
If conventional interpolation methods using 16-bit endpoint components are used, then interpolation accuracy is maintained, but processing time increases
Solution Approach 1:
The interpolation process is divided into two temporal stages: a first stage performing interpolation with lower-bit components (faster, less computationally intensive), and a second stage applying logical processing operations to refine the result. This temporal segmentation reduces processing time by avoiding the need to perform complex 16-bit interpolation operations throughout the entire process.
Solution Approach 2:
The patent performs preliminary interpolation using lower-bit colour endpoint components before applying the final logical processing operations. This preliminary action completes the bulk of the interpolation computation faster, and only then applies the additional logical operations needed for precision, thereby reducing overall processing time while maintaining accuracy.
3Measurement precision
If full 16-bit colour endpoint components are used for interpolation, then colour accuracy is maintained, but hardware circuitry size increases
Solution Approach 1:
The colour endpoint components are segmented into lower-bit portions (8-bit or 12-bit) for the interpolation stage, and only then are the full 16-bit results produced through logical processing. This segmentation allows the hardware circuitry to be sized for the smaller intermediate values rather than requiring full 16-bit处理能力 throughout, reducing overall circuit area while maintaining colour accuracy.
Solution Approach 2:
The patent extracts and processes only the necessary bit portions of the colour endpoints during interpolation, applying logical operations only when needed to produce the final 16-bit accurate results. This extraction approach allows the hardware to be sized for the minimal required bit-width during the main interpolation process, reducing circuit area while preserving colour accuracy in the final output.
Data Source
AI summary
A binary logic circuit performs an interpolation calculation between two endpoint values E0 and E1 using a weighting index i for generating an interpolated result P, the values E0 and E1 being formed from Adaptive Scalable Texture Compression (ASTC) colour endpoint values C0 and C1 respectively, the colour endpoint values C0 and C1 being low-dynamic range (LDR) or high dynamic range (HDR) values. An interpolation unit performs an interpolation between the values C0 and C1 using the index i to generate a first intermediate interpolated result C2; combinational logic circuitry receives the result C2 and performs logical processing operations to calculate the interpolated result P according to the equation: (1) P=└((C2<<8)+C2+32)/64┘ when the interpolated result is not to be compatible with an sRGB colour space and the colour endpoint values are LDR values; (2) P=└((C2<<8)+128.64+32)/64┘ when the interpolated result is to be compatible with an sRGB colour space and the colour endpoint values are LDR values; and (3) P=(C2+2)>>2 when the colour endpoint values are HDR values.