ASTC Interpolation Logic for Smaller Texture Decoding Circuits
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Solution Overview
Problem
Conventional ASTC decoding hardware for texture data is costly in terms of hardware resources and silicon area.
Innovation Solution
A binary logic circuit is used to perform interpolation calculations between ASTC color endpoints using a weighting index, optimizing the interpolation process by operating on lower-bit color endpoint components rather than 16-bit endpoint components, and employing combinational logic circuitry to convert the intermediate result to the final interpolated result.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional ASTC decoding hardware is used to perform interpolation calculations between endpoint values, then accurate texture decoding is achieved, but hardware resources and silicon area are excessively consumed
Solution Approach 1:
The patent changes the bit-depth parameter of the input data by treating 8-bit ASTC endpoint components as 16-bit values through zero-extension. This parameter transformation allows the use of simplified integer arithmetic operations instead of floating-point operations, significantly reducing the hardware resources and silicon area required for interpolation calculations while maintaining the same interpolation accuracy
Solution Approach 2:
The patent substitutes complex floating-point arithmetic operations with simpler integer arithmetic operations. By representing 8-bit endpoint components as 16-bit integers and using integer-based interpolation formulas, the design replaces resource-intensive floating-point units with compact integer arithmetic logic, thereby reducing hardware resource consumption and silicon area
2Manufacturing precision
If conventional interpolation units are used with 16-bit endpoint components, then precise color interpolation is achieved, but circuitry size and processing time are increased
Solution Approach 1:
The patent changes the data representation parameter by treating 8-bit endpoint components as 16-bit integers through zero-extension. This parameter transformation enables the use of efficient integer arithmetic operations instead of complex floating-point operations, reducing circuitry size while preserving color interpolation precision through the use of appropriate integer math formulations
Solution Approach 2:
The patent substitutes floating-point arithmetic operations with integer arithmetic operations. By using 16-bit integer representations of the 8-bit endpoint components and applying integer-based interpolation formulas, the design replaces complex floating-point arithmetic circuits with simpler integer arithmetic logic, thereby reducing device complexity and circuitry size
3Manufacturing precision
If conventional ASTC decoding methods are used, then accurate texel color calculation is achieved, but processing time is increased
Solution Approach 1:
The patent changes the computational parameter by transforming 8-bit endpoint components into 16-bit integer representations. This parameter change enables the use of faster integer arithmetic operations instead of slower floating-point operations, reducing processing time while maintaining texel color accuracy through carefully designed integer-based interpolation algorithms
Solution Approach 2:
The patent substitutes floating-point computation with integer computation. By representing endpoint components as 16-bit integers and using integer arithmetic for interpolation calculations, the design replaces time-consuming floating-point operations with faster integer operations, thereby reducing processing time while preserving computational accuracy
Data Source
AI summary
A binary logic circuit for performing an interpolation calculation between two endpoint values E0 and E1 using a weighting index i for generating an interpolated result P, the values E0 and E1 being formed from Adaptive Scalable Texture Compression (ASTC) low-dynamic range (LDR) colour endpoint values C0 and C1 respectively, the circuit comprising: an interpolation unit configured to perform an interpolation between the colour endpoint values C0 and C1 using the weighting index i to generate a first intermediate interpolated result C2; and combinational logic circuitry configured to receive the interpolated result C2 and to perform one or more logical processing operations to calculate the interpolated result P according to the equation P=└((C2<<8)+C2+32)/64┘ when the interpolated result is not to be compatible with an sRGB colour space, and according to the equation P=└((C2<<8)+128·64+32)/64┘ when the interpolated result is to be compatible with an sRGB colour space.