ASTC Texel Decoder With Shared Colour Endpoint Logic
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Solution Overview
Problem
Existing ASTC decoders require significant chip area due to separate logic circuits for each color endpoint mode (CEM), leading to inefficiency and waste when only one CEM is used.
Innovation Solution
A decoder with a shared logic circuit capable of calculating color endpoints for multiple CEMs, using a set of adders and subtractors arranged as a tree structure, allowing efficient operation across different CEMs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate logic circuits are provided for each color endpoint mode (CEM), then each CEM can be implemented with dedicated optimized logic, but the chip area increases significantly
Solution Approach 1:
The patent implements a universal logic circuit that can perform multiple CEM operations through a single shared structure. The circuit uses multiplexers to select between different CEM operations (CEM0-CEM3) based on control signals, allowing the same physical hardware to execute different color endpoint mode calculations. This eliminates the need for separate dedicated logic circuits for each CEM, thereby reducing chip area while maintaining full functional capability across all CEM variants.
Solution Approach 2:
The patent merges the functionality of multiple separate CEM logic circuits into a single integrated circuit. By combining the adders, subtractors, and control logic for all CEM operations into one shared structure, the design achieves significant area reduction. The merged circuit uses control signals and multiplexers to route data through the appropriate calculation paths for each specific CEM operation, effectively consolidating what would have been multiple discrete logic blocks into one unified unit.
2Area of stationary object
If a shared logic circuit is used for multiple CEMs, then chip area is reduced, but the circuit must handle multiple operations with different requirements
Solution Approach 1:
The patent segments the shared logic circuit into distinct functional units that can be selectively activated. Each CEM operation is broken down into discrete calculation stages (adders, subtractors, multiplexers) that can be independently controlled. This segmentation allows the control logic to enable or disable specific circuit paths based on which CEM operation is currently required, managing complexity by organizing the shared circuit into manageable, independently controllable segments rather than a monolithic structure.
Solution Approach 2:
The patent introduces control signals and multiplexers as intermediary elements that mediate between the shared logic circuit and the different CEM operations. These intermediaries translate high-level CEM operation selections into specific control patterns that route data through the appropriate calculation paths. The multiplexers act as intermediaries that select which input data streams are processed by the shared adders and subtractors, effectively managing the complexity of supporting multiple CEM operations with a single circuit.
Data Source
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AI summary
A decoder configured to decode a texel from a block of texture data encoded according to the Adaptive Scalable Texture Compression (ASTC) format, the decoder comprising a logic circuit for use in calculating colour endpoints in accordance with a plurality of different colour endpoint modes (CEMs), in which: the logic circuit comprises multiple inputs and multiple outputs; and the decoder is configured to: select a colour endpoint mode (CEM) of the plurality of different CEMs; generate, in dependence on the selected CEM, a plurality of input values for inputting to the multiple inputs of the logic circuit, wherein: the plurality of input values are generated such that, when operated on by the logic circuit, the logic circuit will generate at least one intermediate output value at its multiple outputs for use in calculating colour endpoints in accordance with the selected CEM; and for different CEMs of the plurality of CEMs, the decoder is configured to generate, in a different manner, a different plurality of input values for inputting to the same inputs of the multiple inputs of the logic circuit; input the plurality of input values to the multiple inputs of the logic circuit, the logic circuit being configured to operate on said plurality of input values so as to generate said at least one intermediate output value; determine a colour endpoint pair in accordance with the selected CEM in dependence on said at least one intermediate output value; and decode the texel in dependence on the colour endpoint pair.