Asymmetric Access Transistors for Memory Read-Write Margin Optimization
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Solution Overview
Problem
The trend of scaling transistors to smaller sizes and lower power supply voltages in integrated circuits leads to decreased read/write margins for volatile memory elements, posing challenges for reliable device operation, and conventional techniques to ensure memory cell stability result in area overhead and increased manufacturing costs.
Innovation Solution
The use of asymmetric access transistors with varying source-drain resistances, formed through techniques such as asymmetric source-drain implants, silicide deposition, pre-amorphization implants, and stress layers, to achieve different drive strengths during forward and reverse modes, improving read/write margins without redundant resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are scaled to smaller sizes and lower power supply voltages, then device integration density increases, but read/write margins for volatile memory elements decrease
Solution Approach 1:
The patent applies asymmetry by forming access transistors with different threshold voltages - first access transistors have a first threshold voltage and second access transistors have a second threshold voltage that is lower than the first. This asymmetric design allows optimization of read and write operations independently, improving read/write margins while maintaining scaled dimensions.
Solution Approach 2:
The patent implements local quality by applying different pocket implant characteristics to different regions of the access transistors. Specifically, first access transistors receive first pocket implants with first characteristics while second access transistors receive second pocket implants with second characteristics, creating locally optimized transistor properties for different functional requirements.
2Reliability
If conventional techniques are used to ensure memory cell stability (adjusting transistor sizes, asymmetric pocket implants, redundant resources), then read/write margins improve, but area overhead and manufacturing cost increase
Solution Approach 1:
The patent changes the threshold voltage parameter of access transistors through selective pocket implantation rather than changing transistor sizes. By adjusting the threshold voltage of first and second access transistors differently, the patent achieves improved memory cell stability without increasing the physical area of the memory cell.
Solution Approach 2:
The patent uses pocket implantation patterns as templates to create consistent threshold voltage characteristics across multiple transistors. By copying the implantation process with modified parameters for different transistor types, the patent achieves uniform performance characteristics without manual adjustment of each transistor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances read/write stability and performance of memory elements by optimizing the tradeoff between read and write margins, reducing the need for redundant resources and lowering manufacturing costs.
Implementation Method 1
asymmetric source-drain implants
Implementation Method 2
asymmetric source-drain silicide deposition
Implementation Method 3
asymmetric source-drain pre-amorphization implants
Implementation Method 4
stress layers of different types (e.g., tensile-stress-inducing layers and compressive-stress-inducing layers)
Data Source
AI summary
Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. Access transistors may be used to read data from and write data into the storage circuit. An access transistor may have asymmetric source-drain resistances. The access transistor may have a first source-drain that is coupled to a data line and a second source-drain that is coupled to the storage circuit. The second source-drain may have a contact resistance that is greater than the contact resistance associated with the first source-drain. Access transistors with asymmetric source-drain resistances may have a first drive strength when passing a low signal and a second drive strength when passing a high signal to the storage circuit. The second drive strength may be less than the first drive strength. Access transistors with asymmetric drive strengths may be used to improve memory read/write performance.