Asymmetric Alignment Patterns for Off-Cut Semiconductor Substrates
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Solution Overview
Problem
Conventional semiconductor devices on off-cut substrates face deterioration in characteristics due to misalignment caused by decreased recognizability of alignment patterns during the photolithographic process, leading to issues like short-circuit, contact failure, and increased ON-state resistance.
Innovation Solution
The semiconductor device design includes a structure with a first and second semiconductor layer on an off-cut substrate, where the absolute difference in lengths between the second semiconductor layer and the second conductor, or between the conductive surface of the first conductor and the first conductive region, is greater in the off-cut direction, ensuring a larger margin to mitigate misalignment effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional alignment pattern is used on an off-cut semiconductor substrate, then the photolithographic process can be performed, but the alignment pattern recognizability decreases due to misalignment, leading to device characteristic deterioration
Solution Approach 1:
The patent applies asymmetry by designing the alignment pattern with different dimensions in different directions. Specifically, the alignment pattern has a first dimension along the off-cut direction and a second dimension perpendicular to it, where the ratio between these dimensions is deliberately set to be different from 1:1. This asymmetric design compensates for the misalignment effects that occur during photolithography on off-cut substrates, maintaining pattern recognizability and preventing device characteristic deterioration.
2Reliability
If the unit cell size is minimized to maximize channel width per unit area, then the ON-state resistance is reduced, but the alignment margin becomes smaller, increasing sensitivity to misalignment
Solution Approach 1:
The patent resolves this contradiction by introducing dimensional asymmetry to the alignment pattern. Instead of using a symmetric pattern where misalignment in any direction causes failure, the asymmetric pattern provides enhanced tolerance in the critical off-cut direction while maintaining tight dimensions in other directions. This allows the unit cell size to be minimized for low ON-state resistance while the asymmetric alignment pattern provides sufficient alignment margin to prevent misalignment-related failures.
3Reliability
If the margin between semiconductor layers and conductors is increased in the off-cut direction, then misalignment effects are mitigated, but the device area increases
Solution Approach 1:
The patent applies local quality by creating an asymmetric alignment pattern where the margin distribution is non-uniform. The pattern has larger dimensions in the off-cut direction to provide misalignment tolerance, while maintaining smaller dimensions in perpendicular directions to minimize overall device area. This localized adjustment of dimensions in specific directions achieves both misalignment mitigation and area efficiency.
Data Source
AI summary
A semiconductor device is fabricated on an off-cut semiconductor substrate 11. Each unit cell 10 thereof includes: a first semiconductor layer 12 on the surface of the substrate 11; a second semiconductor layer 16 stacked on the first semiconductor layer 12 to have an opening 16e that exposes first and second conductive regions 15 and 14 at least partially; a first conductor 19 located inside the opening 16e of the second semiconductor layer 16 and having a conductive surface 19s that contacts with the first and second conductive regions 15 and 14; and a second conductor 17 arranged on the second semiconductor layer 16 and having an opening 18e corresponding to the opening 16s of the second semiconductor layer 16. In a plane that is defined parallel to the surface of the substrate 11 , the absolute value of a difference between the respective lengths of the second semiconductor layer 16 and the second conductor 18 as measured in the off-cut direction is greater than the absolute value of their difference as measured perpendicularly to the off-cut direction.


