Asymmetric Array Substrate for High-Resolution Displays
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Solution Overview
Problem
The limitation of manufacturing ability restricts the further reduction of sub-pixel sizes, hindering the development of high-resolution display panels.
Innovation Solution
An array substrate with an asymmetric thin film transistor design, where the first and second data line segments define different gaps, allowing for the offsetting of source electrodes to reduce sub-pixel width and increase resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If symmetric thin film transistor design is used, then manufacturing process is simple, but sub-pixel size cannot be reduced further
Solution Approach 1:
The patent applies asymmetry by designing the thin film transistor with non-uniform gap configurations. Specifically, the first gap between adjacent first data line segments is different from the second gap between adjacent second data line segments. This asymmetric design allows the source electrode to be offset, thereby reducing the sub-pixel size while maintaining manufacturing feasibility.
Solution Approach 2:
The patent implements local quality by creating different gap sizes at different locations within the transistor structure. The first gap and second gap are deliberately made different to optimize the local spatial arrangement of the source electrode, enabling compact sub-pixel design without requiring complete redesign of the entire transistor structure.
2Manufacturing precision
If sub-pixel size is reduced to increase resolution, then display resolution improves, but manufacturing ability limitations prevent further reduction
Solution Approach 1:
The asymmetric gap design (first gap ≠ second gap) enables the source electrode to be positioned offset from the center, which reduces the overall sub-pixel width. This approach achieves higher display resolution while remaining compatible with existing manufacturing capabilities, as it optimizes the local geometry rather than requiring complete process overhaul.
3Length of moving object
If asymmetric gap design is implemented, then sub-pixel width is reduced, but data line segment arrangement complexity increases
Solution Approach 1:
The patent deliberately introduces asymmetry in the gap dimensions (first gap ≠ second gap) to enable source electrode offset positioning. This asymmetric configuration reduces sub-pixel width while the data line segments themselves maintain a regular alternating pattern, balancing the trade-off between size reduction and arrangement complexity.
Data Source
AI summary
An array substrate includes a plurality of gate lines, first data line segments, second data line segments, first thin film transistors and second thin film transistors. Each first thin film transistor includes a first gate electrode, a first source electrode and a first drain electrode, and each second thin film transistor includes a second gate electrode, a second source electrode and a second drain electrode. The first data line segment, the second data line segment and the next first data line segment arranged sequentially in a first direction define a first gap and a second gap, where the second gap is greater than the first gap. The first source electrode, the second source electrode and the next first source electrode arranged sequentially in the first direction define a third gap and a fourth gap, where the third gap is greater than the first gap, and the fourth gap is smaller than the second gap.