Asymmetric Assist Device for 3D Memory Leakage Control
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Solution Overview
Problem
Three-dimensional (3D) vertical memory architectures with polysilicon channels face issues such as bulk traps/defects leading to high reverse-biased junction leakage and gate-induced drain leakage (GIDL) currents, limiting operating margins for memory array operations like erase, program, and read.
Innovation Solution
Incorporating asymmetric source and drain assist devices with virtual junctions that allow for controlled biasing during memory operations to shift voltage drops from doped junctions to virtual junctions, optimizing leakage characteristics and improving operating margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical memory architecture with polysilicon channels is used, then memory density is increased, but reverse-biased junction leakage and GIDL currents increase
Solution Approach 1:
An assist device is introduced as an intermediary component between the select device and the memory cell. This assist device includes a gate that can be biased to control the voltage distribution across the channel, thereby mediating the electrical characteristics to reduce leakage currents while maintaining the vertical memory architecture's high density
Solution Approach 2:
The invention changes the electrical parameters by applying controlled bias voltages to the assist device gate. This dynamic parameter adjustment allows shifting voltage drops to optimize the electrical characteristics during different operations (erase, program, read), reducing GIDL currents and junction leakage while preserving memory density
2Quantity of substance
If vertical memory architecture with polysilicon channels is used, then memory capacity is increased, but operating margins are reduced
Solution Approach 1:
The assist device serves as a mediator that improves signal integrity and voltage control in the vertical memory architecture. By inserting this additional control element, the system gains finer control over voltage distribution, which enhances operating margins for read, program, and erase operations while maintaining high memory capacity
Solution Approach 2:
The invention introduces dynamic control capabilities through the assist device gate biasing. The voltage distribution can be dynamically adjusted during different memory operations (erase, program, read), allowing optimization of operating margins in real-time while preserving the high capacity benefits of vertical architecture
Data Source
AI summary
Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.