2R1W/1R1W Cache Allocation for Efficient Data Access
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Solution Overview
Problem
Existing cache designs face a challenge in balancing improved access efficiency with reduced implementation area and cost, particularly when increasing the number of ports for data input and output, which leads to increased control circuits and signal lines.
Innovation Solution
Implementing a cache system with two types of caches having asymmetric structures and different numbers of parallel usable ports, where one cache has two read ports and one write port (2R1W type) and the other has one read and one write port (1R1W type), and using a control circuit to determine data storage based on identification information to optimize data allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of ports for data input and output is increased, then data access efficiency is improved, but the implementation area and cost increase due to increased control circuits and signal lines
Solution Approach 1:
The cache device is divided into multiple independent caches (first cache and second cache), each with different port configurations. The first cache has one read port and one write port, while the second cache has two read ports and one write port. This segmentation allows the system to achieve high data access efficiency through parallel operations without requiring all caches to have maximum port counts, thereby reducing overall implementation area.
Solution Approach 2:
Different caches are assigned different port configurations based on their specific functional requirements and performance characteristics. The second cache with more read ports is optimized for read-heavy workloads, while the first cache with fewer ports handles other operations. This local differentiation allows each cache to be optimized for its specific role without unnecessarily increasing the implementation area of the entire cache system.
2Productivity
If the number of ports for data input and output is increased, then data access efficiency is improved, but the device complexity increases due to increased control circuits and signal lines
Solution Approach 1:
The cache device is divided into multiple independent caches (first cache and second cache), each with different port configurations. The first cache has one read port and one write port, while the second cache has two read ports and one write port. This segmentation allows the system to achieve high data access efficiency through parallel operations without requiring all caches to have maximum port counts, thereby reducing overall implementation area.
Solution Approach 2:
Different caches are assigned different port configurations based on their specific functional requirements and performance characteristics. The second cache with more read ports is optimized for read-heavy workloads, while the first cache with fewer ports handles other operations. This local differentiation allows each cache to be optimized for its specific role without unnecessarily increasing the implementation area of the entire cache system.
Data Source
AI summary
A cache device includes: a plurality of caches that are different from each other in a number of ports that are usable in parallel, and that are each capable of holding data to be used for execution of instructions by an arithmetic operation execution circuit; and a control circuit that controls input and output of data to and from the plurality of caches. When a cache miss occurs for an access request from the arithmetic operation execution circuit, the control circuit determines which of the plurality of caches data transferred from a memory is to be stored in, based on identification information held in a memory, and performs control to store data in the determined cache.