Asymmetric Multilayer Ceramic Capacitor for Acoustic Noise Reduction
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Solution Overview
Problem
Multilayer ceramic capacitors generate acoustic noise due to piezoelectric vibrations when voltage is applied, causing discomfort through sound transmission to printed circuit boards.
Innovation Solution
A multilayer ceramic capacitor design with a ceramic body having dielectric layers, internal electrodes, and external electrodes, where the lower margin part is thicker than the upper margin part, and specific ratios of thicknesses are maintained to minimize noise by forming a point of inflection at the ceramic body's center when voltage is applied.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the multilayer ceramic capacitor uses conventional symmetric structure with equal upper and lower cover layers, then the manufacturing process is simple, but acoustic noise is generated due to piezoelectric vibrations
Solution Approach 1:
The patent applies asymmetry by making the lower cover layer thicker than the upper cover layer. Specifically, the lower cover layer has a thickness of 0.5 to 2.0 times that of the upper cover layer, creating an asymmetric structure that shifts the point of inflection to reduce piezoelectric vibrations and acoustic noise while maintaining manufacturing feasibility
Solution Approach 2:
The patent applies local quality by varying the thickness of cover layers at different locations. The lower cover layer is made thicker locally to counterbalance the piezoelectric effect in the lower portion of the capacitor, while the upper cover layer remains thinner. This localized thickness variation reduces vibrations without requiring complete structural redesign
2Object-affected harmful factors
If the lower margin part is made thicker to reduce noise, then acoustic noise is reduced, but the overall device height increases
Solution Approach 1:
The patent applies parameter changes by optimizing the thickness ratio between the lower and upper cover layers. The lower cover layer thickness is set to 0.5 to 2.0 times that of the upper cover layer, which reduces acoustic noise while controlling the overall height increase. This parameter optimization balances noise reduction with size constraints
3Object-affected harmful factors
If the point of inflection is positioned at the center of the ceramic body, then acoustic noise is minimized, but the active region thickness ratio must be precisely controlled
Solution Approach 1:
The patent applies local quality by creating a specific thickness distribution in the margin parts. The lower margin part is made thicker than the upper margin part, which locally modifies the stress distribution to position the point of inflection at or below the center of the ceramic body, reducing acoustic noise while providing manufacturing tolerance
Solution Approach 2:
The patent applies parameter changes by defining specific thickness ratios for the margin parts. The lower margin part thickness is set to 0.5 to 2.0 times that of the upper margin part, which controls the point of inflection position and minimizes acoustic noise while maintaining practical manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly reduces acoustic noise to less than 30 dB, maintaining capacitance within acceptable limits, while ensuring the point of inflection occurs at or below the soldering height on the printed circuit board.
Implementation Method 1
since these dielectric layers have piezoelectricity properties and electrostrictive properties, a piezoelectric phenomenon may occur and thus cause vibrations among the internal electrodes when AC or DC voltage is applied to the multilayer ceramic capacitor
Implementation Method 2
since these dielectric layers have piezoelectricity properties and electrostrictive properties, a piezoelectric phenomenon may occur and thus cause vibrations among the internal electrodes when AC or DC voltage is applied to the multilayer ceramic capacitor
Data Source
AI summary
There is provided a multilayer ceramic capacitor including: a ceramic body having dielectric layers laminated in a width direction thereof; an active region in which capacitance is formed, by including first and second internal electrodes alternately exposed to end surfaces of the ceramic body while having the dielectric layer interposed therebetween; an upper margin part prepared above the active region; a lower margin part prepared below the active region on the dielectric layer and being thicker than the upper margin part; and first and second external electrodes, wherein, when half of thickness of the ceramic body is denoted by A, thickness of the lower margin part is denoted by B, half of thickness of the active region is denoted by C, and thickness of the upper margin part is denoted by D, 1.047≦(B+C)/A≦1.562 is satisfied.