Asymmetric Channel Rows in 3D NAND Memory
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Solution Overview
Problem
The existing three-dimensional nonvolatile memory devices face challenges in achieving improved operational reliability and integration due to limitations in their structure and manufacturing processes, particularly in the stacking of memory cells and interlayer insulating layers.
Innovation Solution
A semiconductor device with a stack structure featuring asymmetrically arranged channel rows, including both channel patterns and dummy channel patterns, which allows for a source connection structure that penetrates the stack, enabling efficient data storage and improved integration by varying the number of channel rows in different memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If three-dimensional nonvolatile memory devices are designed with vertically stacked memory cells to improve integration, then the degree of integration is improved, but the operational reliability deteriorates due to structural limitations and manufacturing process challenges
Solution Approach 1:
The patent applies asymmetry by configuring different numbers of channel rows in first and second memory blocks. Specifically, the first memory block has a first number of channel rows while the second memory block has a second number of channel rows, creating an asymmetric structure that optimizes reliability for each block while maintaining high integration. This asymmetric design allows tailored optimization of operational parameters for different memory blocks within the same three-dimensional stacked structure.
2Adaptability or versatility
If the number of channel rows is increased to improve data storage capacity, then the degree of integration is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory device into multiple independent memory blocks, where each block can have a different number of channel rows. This segmentation allows the manufacturing process to handle complex high-capacity requirements by breaking them down into manageable blocks, where each block can be optimized and manufactured separately before being integrated into the final device.
3Device complexity
If symmetric structure is used for simplicity in design, then the device complexity is reduced, but the operational reliability deteriorates due to inability to optimize different memory blocks independently
Solution Approach 1:
The patent applies universality by creating a modular memory block design that can be replicated and configured in different numbers across the device. Each memory block serves as a universal unit that can be independently optimized while maintaining the same basic structure, allowing the system to achieve both design simplicity through modularity and reliability through configurable variations.
Data Source
AI summary
A semiconductor device includes: a stack structure; a source connection structure penetrating the stack structure; n first channel rows located at one side of the source connection structure, the n first channel rows including channel patterns; and n+k second channel rows located at the other side of the source connection structure, at least one channel row among the n+k second channel rows including dummy channel patterns, wherein the n and k are integers.