Asymmetric Chip-to-Chip Interconnect for Mixed Reliability and Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In high-speed data transmission systems, the standard interconnect approach faces reliability issues at high data rates, while the differential interconnect approach requires higher clock speeds that not all devices can handle, leading to limitations in data capacity and reliability due to differing maximum operating frequencies of components.
Innovation Solution
Implementing asymmetric signaling over a parallel bus, where data transmission occurs as standard interconnects in one direction and differential interconnects in the other, allowing for varying data rates and clock speeds to match the capabilities of each device, thereby maintaining data capacity and enhancing reliability without exceeding maximum operating frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If differential interconnect approach is used to improve data reception reliability, then reliability is improved, but clock speed requirements increase beyond what not all devices can handle
Solution Approach 1:
The patent applies asymmetry by implementing different interconnect approaches for different transmission directions. Specifically, one direction uses differential interconnect (TX0/D0, TX1/D1) while the other direction uses standard interconnect (TX2/D2, TX3/D3). This asymmetric configuration allows each direction to be optimized independently, enabling reliable data reception where differential signaling is applied without requiring all devices in the system to operate at high clock speeds.
2Adaptability or versatility
If standard interconnect approach is used to maintain device compatibility, then device compatibility is maintained, but data reception reliability deteriorates at high data rates
Solution Approach 1:
The patent applies local quality by assigning different interconnect characteristics to different channels based on their specific requirements. Channels requiring high reliability at high data rates are configured with differential interconnect, while other channels use standard interconnect. This localized optimization allows each channel to have the appropriate signaling type for its specific needs, improving overall system reliability without compromising device compatibility.
3Productivity
If higher clock speeds are used to increase data capacity, then data capacity increases, but device limitations are exceeded
Solution Approach 1:
The patent applies dynamics by allowing different clock speeds for different directions of data transmission. The differential interconnect direction can operate at higher clock speeds to achieve greater data capacity, while the standard interconnect direction operates at lower clock speeds compatible with device limitations. This dynamic, direction-specific clocking strategy optimizes data capacity where possible while respecting device constraints.
Data Source
AI summary
Methods and apparatuses to transfer data between a first device and a second device are disclosed. In various embodiments, an apparatus includes a first device and a second device. The first device includes at least one first non-differential transmitter coupled to a first channel, at least one second non-differential transmitter coupled to a second channel, and at least one differential receiver to receive a data bit and its complement on the first and second channels in parallel. The second device includes at least one first non-differential receiver coupled to the first channel, at least one second non-differential receiver coupled to the second channel, and at least one differential transmitter to transmit a data bit and its complement on the first and second channels in parallel. Other methods and apparatuses are disclosed.