Chip Package With Asymmetric Die Heights And Planarized Molding
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Solution Overview
Problem
New packaging technologies for semiconductor devices face manufacturing challenges in achieving high integration density and functional improvements while maintaining reliability and structural integrity, particularly in forming chip packages with varying die heights.
Innovation Solution
The method involves bonding semiconductor chips and stacks of different heights over a substrate, using conductive bonding structures and molding compound layers to encapsulate and protect the dies, with a package layer that is planarized to expose the top surface of the taller chip while protecting the shorter chip stack from damage during thinning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips and stacks of different heights are bonded over a substrate, then integration density and functionality are improved, but manufacturing complexity and reliability risks increase due to varying die heights
Solution Approach 1:
The patent segments the chip package into distinct height levels, with first chip stacks having a first height and second chip stacks having a second height different from the first. This segmentation allows different functional requirements to be met at different heights while maintaining overall package integrity and managing manufacturing complexity through structured organization.
Solution Approach 2:
The patent utilizes the vertical dimension by bonding chip stacks of different heights along a first direction, creating a three-dimensional package structure. This dimensional approach enables higher integration density by stacking chips vertically rather than only placing them side-by-side in a single plane.
2Adaptability or versatility
If chip stacks of different heights are bonded together, then functional integration is improved, but structural integrity and reliability deteriorate due to height mismatches
Solution Approach 1:
The patent applies local quality by providing different heights for different chip stacks based on their specific functional requirements. First chip stacks have a first height suitable for their function, while second chip stacks have a second height optimized for their function, allowing each component to operate at its optimal structural configuration while maintaining overall reliability.
Solution Approach 2:
The patent employs asymmetry by intentionally creating chip stacks with different heights rather than uniform dimensions. This asymmetric structure allows the package to accommodate diverse functional requirements of different chip types while maintaining structural integrity through careful design of the bonding interfaces and supporting structures.
3Quantity of substance
If varying die heights are used in chip packages, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by establishing predetermined height relationships between different chip stacks before the bonding process. The first chip stacks are designed with a first height and the second chip stacks with a second height in advance, allowing manufacturing processes to follow established specifications rather than requiring real-time adjustments, thereby maintaining precision while achieving high integration density.
Data Source
AI summary
Structures and formation methods of a chip package are provided. The chip package includes a chip stack including a number of semiconductor dies. The chip package also includes a semiconductor chip, and the semiconductor chip is higher than the chip stack. The chip package further includes a package layer covering a top and sidewalls of the chip stack and sidewalls of the semiconductor chip.